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Reverse bias techniques for high-end automotive MCUs

04 Jun 2015  | Stefano Pietri, Chris Dao, Jouxiang Ren, Scott Herrin, Anis Jarrar

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Modern microcontrollers' computational cores usually employ digital gates with different flavours of threshold voltages Vt (e.g., high Vt, standard Vt, and low Vt), and libraries with different gate channel lengths in order to optimise the performance/power ratio.

Using shorter channels/low threshold will increase maximum performance at the expense of higher leakage, and vice versa, using longer channels/high threshold will lower leakage at the expense of lower performance. In a high-end automotive MCU based on a standard CMOS process, leakage can account for as much as 50% of the total power budget at 150°C.


Figure 1: Standard gate supply/well connection vs. reverse back biased gate.


Techniques like power gating or dynamic frequency voltage scaling work well to reduce average consumption, but they are less effective to reduce peak consumption. Automotive real time application require having maximum performance available at any time, therefore in order to reduce power consumption at hot temperatures, we introduced RBB (Reverse back bias) for MCU's in bulk process at the 55 nm node. RBB is quite common for MCU's implemented in SOI (Silicon on Insulator) process because of the lower risk of latch-up.


Figure 2: Process corner distribution and when RBB becomes useful.


A standard Sea of Gates (SOG) implementation has core logic cells n-MOS devices either in p-substrate or p-well, with n-MOS back-gate connection shorted to VSS; the p-MOS devices are in an n-well with back-gate connection shorted to VDD core supply. In RBB configuration, the p-well will be lowered below the VSS level, and the n-well will be elevated above VDD level, with the net effect of increasing the effective source—body voltage for n-MOS and p-MOS transistors, respectively (figure 1).

In simplified terms, channel leakage is a subthreshold current and it increases exponentially with Vgs (gate to source voltage), while ON saturation current (IDSsat) is proportional the square of Vgs. Therefore increasing the Vt by depleting the body of a MOS device will reduce leakage faster than IDSsat. By independently controlling the bulk terminal (i.e. the p-well and n-well of the core logic transistors), we can modulate leakage and IDSsat reaching an optimal point: high logic performance at a reduced total power consumption.

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