RTL synthesis engine offers 10-fold design productivity05 Jun 2015 | Julien Happich
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Cadence Design Systems has announced its next-generation register-transfer level (RTL) synthesis and physical synthesis engine. According to the company, the Cadence Genus synthesis solution integrates a multi-level massively parallel architecture that promises to offer up to 5X faster synthesis turnaround times while scaling linearly beyond 10M instances.
In addition, the tool's novel physically aware context-generation capability is said to reduce iterations between unit- and chip-level synthesis by 2X or more, factoring up to a to 10X improvement in RTL design productivity.
The tool is architected around three levels of parallelism together with adaptive scheduling so as to support the timing-driven distributed synthesis of complex designs across not only multiple cores but also across multiple machines, all transparently to the user.
What's more, the complete timing and physical context for any subset of a design can be extracted and used to drive RTL unit-level synthesis with full consideration of chip-level timing and placement, significantly reducing iterations between chip-level and unit-level synthesis runs.
The Genus synthesis solution shares a unified global routing with Cadence's Innovus Implementation System, enabling a tight correlation of both timing and wirelength to within five per cent from synthesis to place and route.
For design optimisation, it incorporates an innovative data path optimisation engine that concurrently considers many different data path architectures across the whole design and then leverages an analytical solver to pick the architectures that achieve the globally optimal performance, power and area (PPA). This engine delivers up to 20 per cent reduction in data path area without any impact on performance, claimed Cadence.
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