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How to supervise, power-sequence an SoC

29 Jun 2015  | Eric Schlaepfer

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Microprocessors, microcontrollers, and systems on chips (SoCs) typically require a reset pulse to initialise properly. Many of these devices also use separate I/O- and core-voltage supplies. When you use multiple supplies, you must turn them on in a specific sequence to prevent the circuits from ending up in an unknown state or burning out due to unexpected current paths. You should also monitor the voltages to ensure that the device does not come out of reset until both voltages settle to levels within the operating-voltage range.


Figure 1: This circuit provides a microprocessor or an SOC with a clean reset pulse.


A previous design idea presents a circuit performing the reset function (Reference 1). Unfortunately, this circuit suffers from a number of limitations. For example, it does not monitor the voltage on the 3.3V rail. The 3.3V rail acts as a reference, so the 1.8V rail suffers from poor monitoring accuracy. Further, the reset delay may not be present if you sequence the power rails in the reverse order, and the reset pulse has a glitch that could cause problems with the S0C. Finally, the resetdelay capacitor may reset incorrectly if you rapidly cycle power.

The circuit in figure 1 uses a reset IC to provide a glitch-free reset pulse with a well-defined pulse width. It accurately monitors both the 3.3 and the 1.8V rails. You adjust resistors R1 and R2 to set the monitoring threshold for different core voltages using the equation VTH=1.263X(1+R1/R2), where VTH is the threshold voltage. You adjust C1 for different pulse widths. You calculate C1 using the following formula: C1= (t−275X10−6)/(2.73X106), where t is the desired delay in seconds and C1 is in farads.


Figure 2: Sequence two power supplies using R1 and C1 to set the delay.



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