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Revisiting the history of jitter: Time-interval error

03 Aug 2015  | David Maliniak

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Behind most, if not all, of these efforts to better analyze and quantify jitter is the Dual-Dirac model covered in the previous installment of this blog series. But, during the 1990s, another approach to jitter measurement began taking root: time interval error (TIE) (figure 1).

At its core, jitter measurement is about comparing when an edge actually arrives to when it's expected to arrive. For any given edge, the difference between the two is its TIE value. If you analyze a bunch of edges in your waveform and plot them, you create a TIE track, or, essentially, a waveform of all those individual TIE values (figure 2).


Figure 2: The TIE track (in yellow at top) lends itself to further analysis of slowly-varying jitter elements.


From this data, other forms of analyses become available, and these forms were facilitated by the advent in the 1990s of the phase-locked loop (PLL) for clock-data recovery. With a USB signal, you have data only without a clock, and you must determine the underlying bit rate. USB is a good example of how the PLL was brought to bear (in concert with some applied math). Chips began to be built into oscilloscopes that would bring together that math and engineering to pull out that wandering, low-frequency jitter based on the bit rate. It's a little like listening to music: We tap our feet to the beat, whether faster or slower, but we track it. That's what the PLL does in clock recovery for a clockless signal.

We'll look at some of the advances in jitter analysis that stemmed from the concept of PLL-based clock-data recovery in subsequent posts.


About the author
David Maliniak joined Teledyne LeCroy in 2012 as Technical Marketing Communications Specialist. He worked for over 30 years in the electronics OEM B2B press, most recently as Test and Measurement and EDA Technology Editor at Electronic Design magazine. Maliniak holds a BA in Journalism from New York University.


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