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Circuit allows testing of sample-and-hold amps

07 Aug 2015  | Marian Stofka

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You can use the previous equations to find the values of the voltage pedestal and the peak voltage drop. A 75% duty cycle is a convenient value. The following equations are valid for this duty cycle: VINJ=6[ΔVOUT]–2/3[Δ]–16/3VSTAT, and VDROPPEAK=16[–[ΔVOUT]+1/3[Δ]+2/3VSTAT]. You must find the optimal repetition rate, fREP, of the logic-control signal. As the optimal repetition rate increases, the difference in output voltage from the input is almost purely due to dc voltage offset plus the voltage pedestal: (–VSTAT)/(VOUT–VSTAT)≈3. The following equation finds the maximum value for the optimal repetition rate: fREP≤(0.01/4)×1/(tON–tOFF), where tON and tOFF are the on and off times, respectively. This equation ensures that the difference in values between the turn-on and turn-off times of the sample-and-hold amplifier's internal analogue switch won't affect the accuracy of the precision 25 and 75% duty cycles by more than 1%.

If you evaluate the equation for a high-performance analogue switch, such as the Analog Devices ADG1213, you get a repetition rate of 33kHz or less. The difference due to voltage drop prevails at low-value repetition rates. In this case, the repetition rate can be the value of the frequency at which –VSTAT≤1/10×VINMAX, where VINMAX is the maximum input-voltage range. The best way to determine the lower limit of the repetition rate is through experimentation.


Figure 2: A sample-and-hold amplifier's holding capacitor experiences a voltage drop due to leakage and bias currents plus a voltage step, which results in a difference between the amplifier's output and input voltages.


A tested sample-and-hold amplifier using the circuit in figure 2 uses a supply voltage of –1V, a drain-to-drain voltage of 5V, and a supply voltage of 3.3V for logic circuits in the pulse generator. Two sets of measurements at 25, 75, and 100% duty-cycle values for the AGD1213's internal switch control used input voltages of 0 and 2.5V. You will measure the output-voltage difference, approximately –0.0366 mV, and the pedestal voltage, approximately –0.0333 mV, at a repetition rate of 1.762kHz. The value of the residual effective charge injection, QINJ, into the hold capacitor, CH=2 nF, is QINJ=CH×VINJ. The value is negative and doesn't exceed –75 fC. The following equation defines the difference of charge injection within the 2.5V range of input voltage: ΔQINJ=QINJ(2.5V)–QINJ(0V) and yields a value of –6.7 fC. The following equation determines the residual effective leakage current from the acquired values of peak voltage drop at a repetition rate of 160Hz: ILEAK=CH×VDROPPEAK×fREP, where ILEAK is the leakage current. A leakage current at the input voltage of 0V is approximately 17 pA, and a leakage current at the input voltage of 2.5V is approximately –17 pA.


Reference
"Low Capacitance, Low Charge Injection, ±15 V/+12 V iCMOSTM Quad SPST Switches," Analog Devices Inc, 2005.
About the author
Marián Štofka is with Slovak University of Technology in Bratislava, Slovakia


This article is a Design Idea selected for re-publication by the editors. It was first published on July 15, 2010 in EDN.com.


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