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Benefits of DDR interface gate-level simulation

11 Aug 2015  | Abhinav Gaur, Kushagra Khorwal

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Considerations for the physical design team
Partitioned Design – Skew between chip_top and Block
Generally, DDR controller is implemented as a hard block in SoCs. The data channels and strobes traverse through a long region physically based on the pad locations. DDR controller Block and Pads need to be abutted to each other so that the data to/from the pads is fed directly from the DDR block without any chance of net or cell variation. Many times this requirement may not be feasible due to physical / floorplan constraints. In those cases, skew balancing should happen looking at the channels routed at both chip_top and inside block. For e.g., consider channel A is placed far apart, while channel B is nearby DDR controller block. The skew balancing algorithm should take the maximum distance amongst all data channels for balancing. There should be buffers placed at regular intervals both at chip-top and inside block. All the spiral routing on channel B (near the pad) should be done inside DDR controller block looking at the max distance provided by channel B. Consider figure 1 which shows the arrangement where the skew needs to be met for all data channels through the controller and PHY to PADS. Figure 2 presents a scenario where part of the channel is sitting on chip-top and part inside block.


Figure 1: Data Transmission between controller and DDR PHY.



Figure 2: Data Transmission between controller and DDR PHY.


OBE assertion and de-assertion
Obe (Output Buffer Enable on Pads) assertion and deassertion should be timed properly across corners w.r.t Data / DQS. Obe Assertion and De-assertion plays an important role in Read DQS Gating, Preamble and Postamble times. These timings could be modelled in terms of Skew checks between DQS Data and OBE signals.


Pads configurability
The DDR pads should be such that they provide delay and duty cycle configurability across PVT. This could be used for both debug and functional purposes in field. The resolution of the delay could be as lesser as possible. This is an additional feature which could help in,

 • Improved Eye diagrams using Bit Skewing and De-Skewing on Data channels.
 • Improved Duty Cycle for Skewed N and P lots of Silicon


Rise/Fall on both Data and Strobe
For meeting Skew across PVT within a certain limit, both rise fall edges of data and strobes must be looked into. One might ask since data and dqs are generated from the same clock edge, only rise-fall of data (from symmetric eye) should be considered with respective edge of strobe. But, this isn't true. The reason is that memory would always capture the launch data from controller at the next T/4 shifted edge. So, if controller is launching the data on rise edge, it should get captured on the fall edge at memory. Hence, the skew should be met across all rise and fall combinations. Figure 3 explains this.


Figure 3: Data flow between controller and memory. 2nd diagram shows T/4 shifted data at memory.



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