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Instruction set architectures go head to head: RISC vs. CISC

07 Aug 2015  | Bernard Cole

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A recent study in the ACM Transactions on Computer Systems has revealed that processor instruction set architectures, whether reduced (RISC) or complex (CISC), are irrelevant to basic power and performance in today's designs, particularly in relation to either the ARM or Intel processors. However, there may be reasons to believe that a new CISC ISA, developed for modern compilers without the limitations of compatibility with low level legacy code, could be more effective than either alternative.

Imsys has taken that leap of faith and is giving CISC another try. The company has begun extensive evaluation of a 3.5mm2 test chip with a dual core, CISC-based processor architecture with on-chip main memory for software and data. It is fabricated in 65nm CMOS.

To make it easy for developers to evaluate and port existing code, the processor incorporates a CISC ISA optimized for use with compilers based on LLVM for C/C++ (and other languages). The chip's ISA currently has about 1,100 opcodes, with instruction sizes in the 1-10 byte range, with an average of 3.15 bytes. According to Stefan Blixt, CTO at Imsys, the new instruction set is close to the LLVM intermediate representation (i.e., the starting point for the compiler backend), which results in more efficient translation and higher code density than when targeting legacy CISC or RISC instruction sets.

Blixt said the 65nm chip is a proof-of-concept, many-core cell design with a five port network on chip (NoC) router for applications where main memory has to be distributed such that each cell has tasks running on the cores. Code density of the core architecture will determine how many cores the final implementations will have.

Imsys test chip

Imsys 1.875mm x 1.875mm test chip is a dual-core CISC SoC with 256KB ROM + 160KB RAM and a 5-port NOC router.

With the cell used in this test chip, the number of cores can be more than 100. However, at the 22nm process node Imsys evaluations have determined that the number supported can be as high as 1,000, all of them being general purpose cores capable of executing their tasks independently or together by communicating over the NoC interconnect.

According to Blixt, the real power of the CISC approach will be most apparent in small footprint IoT designs, especially when compared with typical ARM-based processors such as Freescale's Kinetis L family. "In our evaluations against published specs on that family of devices, our core has lower power consumption but does more than 3.5 times as much useful work per second, since the maximum frequency is 3.5 times higher for our device and we do more such work per clock cycle. Actually the dual core processor works at up to twice the specified frequency, so for the chip as a whole the factor could be as high as 14.6 times."

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