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Nanotech experts team up to drive Moore's Law forward

28 Aug 2015  | Jessica Lipsky

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"Lithography is the most expensive step in creating a chip, which has drawn a lot of companies in here to share the cost," Fancher said.

To mitigate development costs, competitors in the CNSE clean room will use the same tools and can lease time for when wafers are being processed with their IP. Companies can also collaborate, creating CNSE-owned IP.

At Semicon West this year, CNSE highlighted developments to its 450mm wafer platform as part of the Global 450mm Consortium (G450C), including the addition of a 120w Gigaphoton ArF laser and Nikon 450mm 193nm immersion scanner. The college has 450mm machine running in house the size of a large shed with its guts hanging out, although the process isn't up to speed for next-generation nodes.

Nikon 193nm

Installation of a Nikon 193nm immersion system.

"While you can use immersion to do 10nm structures, you have to use a lot of tricks to do it," Fancher said. "We're demonstrating process modules and process flows to get them to integrate with each other. We're doing that with TSMC, Intel, IBM, GlobalFoundries and Samsung."


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