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Seven steps to a winning analogue ASIC

09 Sep 2015  | Bob Frostholm

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What if you need to make a design change midway through the ASIC development process? This happens frequently. Things can go wrong and often do. Requirements can change unexpectedly. Make sure both you and your analogue ASIC supplier understand this and have a corrective action plan. There may be additional charges, depending on the changes you are requesting and how far along the design is. If the chip needs a re-spin and you didn't change your requirements, it's the responsibility of the ASIC supplier to do it without charging extra. Remember, it's the ASIC supplier's responsibility to hire and retain the best design talent; use the highest quality subcontractors for silicon fabrication and package assembly. If there are any problems there, they own it, not you.


Analogue vs. Digital ASICs NRE
This is where analogue differs greatly from Digital in the ASIC world. Parametric performance in the digital world is almost a no brainer. Every function that connects to another function has a well-defined interface. It's either a logic 1 or a logic 0 and each of these has a well-defined min and max limit. This is not the case with analogue. Analogue design requires that thousands, maybe tens or hundreds of thousands, of device interconnects on the chip must match exactly.

What does this mean for NRE? What it means is that when specifying and designing analogue ASICs, there is significantly more CUSTOM ENGINEERING involved. It also means that much more care and consideration must be put into the budgetary proposal being prepared for the customer. It's not unusual for back and forth technical Q&A to take place between the lead ASIC designer assigned to the project and the customer's point person. The ASIC supplier needs to know everything there is to know about the design; its application, its environment, its architecture and more. This process of thoroughly understanding the customer's needs can take weeks, sometimes months before a legitimate proposal can be offered. When quoting a moderate to complex analogue ASIC, it's not unusual for the ASIC supplier to invest $10-$20K of their own resources just to provide a proposal. They should not be charging you for this effort. It's part of the cost of doing business.

Moreover, while the ASIC design manager is evaluating the basic ASIC itself, another ASIC team is looking into how this chip is going to be tested. What levels of precision are needed? Are there any special needs such as data acquisition functions? What power management blocks are involved? Are there any special noise requirements? Power up sequences? Are there any high voltage requirements that need to be addressed? At the end, does a special analogue tester need to be designed and built beyond a typical load board?

The cost of the NRE and Tooling can vary greatly. Variables include the design complexity (man hours required to design and layout the chip), mask costs (determined primarily by the lithography of the wafer process; 0.18um, 0.35um, 0.5um, etc.), wafer costs (determined in part by the wafer size (150mm, 200mm, etc.) and by special needs (number of layers, SOI, cavity etch for sensors, etc.). Your analogue ASIC supplier will review with you any options and trade-offs you may wish to consider that might minimise any of these costs.

Another thing to consider is NRE and Tooling Rebates. Ask you analogue ASIC supplier if they offer a rebate program for the up-front costs associated with developing the chip. These are implemented during the early production lifetime of the product and are a means of further equalising the cost of an ASIC with that of a standard product. It essentially has the effect of making the front end costs appear as a loan that gets paid back as production is consumed rather than a sunk cost.


Supporting production capability
Supporting all of this is production capability. During this proposal development phase, the ASIC design manager also investigates the realm of possible wafer fabrication process that are suitable to produce your design, selecting the one she/he feels is a best fit solution. The IC will be designed to meet the specific requirements of this silicon process. With rare exception, silicon fab processes cannot be changed or modified. The burden is 100 per cent on the ASIC design team to get it right. If you remember only one thing from this paper, it is to NEVER SEPARATE DESIGN FROM PRODUCTION. Doing so sets the stage for conflict when something goes wrong. Is it a design problem or a manufacturing problem? Unless your analogue ASIC supplier is developing or modifying a process, when a performance issue arises in the initial silicon samples, 99 times out of 100 it will be a design problem. Yet independent analogue design houses will argue the contrary, and you, the customer, are stuck in the middle. This is not where you want to be. Even if you have lots of experience managing the backend for digital ASICs, you should always use full service or turn-key supplier for analogue ASICs.

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