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Achieve power distribution flexibility with USB PD

18 Sep 2015  | Paul Pickering

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The PHY supports cable ID detection/identification and loopback modes. The PHY includes a 24MHz FSK modulator/demodulator and provides integrated terminations. The on-chip microcontroller manages the I/O and implements the Power Delivery local policy engine and device manager.

The SPI ROM controller is used by the microcontroller for optional external code execution from ROM. A One Time Programmable (OTP) ROM is integrated in the UPD1001,which is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges and offered in a 32-pin SQFN package.

The PTN5100 from NXP is a single-port USB Type-C Power Delivery (PD) PHY and protocol IC that provides a USB-C Configuration channel interface and USB PD Physical and Protocol layer functions to a System PD Port Policy Controller.

The device is targeted for a wide range of platforms including standard notebook PCs, desktop PCs, tablets and smart phones, as well as PC accessories such as docking stations, monitors, and cable adapters. It can support system power provider, consumer, or combination functions; programmable registers allow operation as UFP, DFP or DRP as discussed above.

The PTN5100 implements a VCONN low RON switch with register-programmable Forward Current protection feature. The VCONN switch also provides reverse current protection to detect reverse current flow into the system whenever an inductive or charged cable is unplugged from the connector. It provides either an SPI or I2C interface for system host control; the choice of interface is pre-configured at the factory.

Cypress Semiconductor has a broad range of USB-C and USB PD products, including the CCG1 USB-C controller with integrated PD, shown in figure 5.

The CCG1 supports provider and consumer roles and all USB PD power profiles. It incorporates a 48MHz ARM Cortex-M0 32bit MCU with 32KB flash and 4KB SRAM. Integrated functional blocks include a 12bit, 1-Msps ADC for VBUS voltage and current monitoring, dynamic over-current and over-voltage protection, 2 configurable 16bit TCPWM1 blocks, and up to 8 GPIOs. Serial communications include I2C master or slave, SPI master or slave, or UART.

The CCG1 operates from 1.71-5.5V and offers several low power modes: Sleep (1.3 mA); Deep Sleep (1.3µA); Hibernate (150 nA); and Stop (20 nA). A variety of packages are available, including 40-pin QFN, 28-pin SSOP, 35-ball CSP, and 16-pin SOIC.


Figure 5: The CCG1 (source: Cypress Semiconductor)


Conclusion: One spec to rule them all?
The USB Power Delivery Specification adds powerful new functionality to the basic USC serial communication function. When combined with the USB-C interface specification and the USB 3.1 high-speed data protocol, it points the way forward for serial communication. Together, the three specifications are designed to accommodate future upgrades, and commercial products (such as the new Apple Macbook Pro) are already beginning to include one or more of the specs as standard features.

As the USB PD becomes more widely adopted, it's expected that it will lead to a rethinking of power distribution for consumer devices, as illustrated in figure 1, and render unnecessary untold millions of power bricks and wall warts. The world's landfills will be breathing a collective sigh of relief!


About the author
Paul Pickering has over 35 years of engineering and marketing experience in the electronics industry, including time spent in automotive electronics, precision analogue, power semiconductors, flight simulation and robotics. Originally from the North-East of England, he has lived and worked in Europe, the US, and Japan. He has hands-on experience in both digital and analogue circuit design, embedded software, and Web technologies. He has a B.Sc. (Hons) in Physics & Electronics from Royal Holloway College, University of London, and has done graduate work at Tulsa University. In his spare time he plays and teaches the guitar.


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