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Examining 3D chip/package/PCB co-design

29 Sep 2015  | Humair Mandavia

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Using this technology, multiple ICs can be imported into the co-design environment and connected together. The 3D, multi-design environment more intelligently manages the routing interdependencies of complex packages such as PoPs and SiPs. This new approach provides focused design rule checks for SiPs with real-time 3D design and support for complicated bond wire placement of stacked LSIs. Engineers can use the co-design environment to ensure that bond wires meet the spacing requirements at any angle, and that the 3D bond wire profile meets the manufacturing specification.


Figure 4: Managing complex 2.5/3D IC designs with TSVs.


This new approach greatly improves the floorplanning and routing of TSV-based designs such as 3DIC stacked chips and silicon interposers. Engineers can import existing databases (from OpenAccess, GDS or LEF/DEF files) or use the design environment to generate TSVs. Automatic or manual routing can be executed using imported or manually generated manufacturing and design rules. Preplaced TSVs can be automatically routed while unplaced TSVs can be placed and routed. The 3D environment supports large datasets and allows designers to see complex escape and routing structures.



Figure 2: Verify signal performance with integrated signal and power integrity analysis.


As changes are made at any level of the system, designers can view the effects from a signal integrity, power integrity, or thermal point of view. Multi-discipline, multi-physics analysis can be performed with best-in-class solutions from solution providers such as Keysight Technologies, ANSYS, AWR, CST, and Synopsys. The co-design environment enables signal traceability across the complete system. Signal paths can be reviewed and analysed as they cross design and component boundaries from drivers through the system interconnect to receivers. Intelligent and integrated schematic- or layout-based simulation environments support multiple design flows.


Conclusion
Chip/package/board co-design provides a unified design approach that enables designers to consider the system-level impact of each design decision to reduce design costs, improve performance, reduce uncertainty, and accelerate schedules. Designers can consider IC/package/PCB issues concurrently to design well integrated products with optimal signal performance while reducing RDL, interposer/substrate, and package layer counts to reduce costs and time to tape-out.


About the author
Humair Mandavia is a Senior Technical Marketing Manager.


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