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Reusing UVM RTL tests for gate level simulation

13 Oct 2015  | David Vincenzoni

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Where the POLY_GEN8 is 0x03. The function can be extended for CRC32 using the POLY_GEN32 = 0x2608EDB.

The use of this methodology greatly simplifies data management on the scoreboard; since the data checking is performed on a serial interface, it is independent of the data size of the microprocessor bus, which can be 8, 16, 32 bits or more. Below is an example of a scoreboard.



Full duplex synchronous interface
In case of a full duplex synchronous interface such as an SPI, we can have two possible modes: the peripheral is slave, or the peripheral is master.

When the peripheral is slave, the transactions are initiated by the external UVM VC. The full duplex modes imply the necessity of sending and receiving data at the same time. Since we want to avoid data generation on the SoC side (no cabled data on C code), there is a systematic delay on valid data. This delay shall be implemented on the scoreboard in order to properly compare the data exchanged.


Figure 4: Full Duplex data sequence for Slave Mode.


Figure 4 shows an example of a data sequence exchanged between the master (UVM VC) and slave (peripheral). The first symbols transmitted by the peripheral are 'do not care' for the scoreboard and are thus discharged. The microprocessor takes some time to get the data from the buffer and compute the CRC. After a while, the data are ready and the exchanging continues with the random generation from the UVM VC and pseudo random data from the peripheral side (CRC computed over Dx).

We can have an automatic symbol synchronisation, by using a conventional 'do not care' data (e.g., zero). Of course, this data shall not be generated by the UVM VC. The peripheral on the SoC will send zero until the CRC data are ready, and the UVM VC terminates with enough zero symbols for completing the matching in the scoreboards.

When the peripheral is master, the transactions are initiated by itself through the microprocessor.


Figure 5: Full Duplex data sequence for Master Mode.


The data flow is quite similar to the case of slave mode. Figure 5 shows an example of a data sequence exchanged between the master (peripheral) and slave (UVM VC). The first symbols transmitted by the peripheral are 'do not care' for the scoreboard. The UVM VC replies with random symbols Dx that the microprocessor uses to compute the pseudo random data transmitted by the peripheral. As above, the yellow highlighted symbols are the one compared in the scoreboard.


Half-duplex interface
In case of half-duplex interface such as I2C, we can have two possible modes: the peripheral is slave, or the peripheral is master.

When the peripheral is slave, the transactions are initiated by the external UVM VC. The half-duplex modes are based on a communication protocol where the master sends commands requesting data as a reply or sends data to the dedicated slave.

As for full duplex mode, it is necessary to define a good flow that avoids the data in C code (not random) and keeps the data checking simple:

 • Start the transaction by sending the write command. The UVM VC will start sending data packets. These data are added in the scoreboard after the computation of CRC.
 • The received data are used by the DUT as 'reply of read' command. The microprocessor computes the CRC on received data and prepares the data packets for reply.
 • The UVM VC sends the read command. The peripheral start sending the previously prepared data. These data are added in the scoreboard for matching.

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