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DSP core ups mobile imaging performance

08 Oct 2015

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Cadence Design Systems Inc. has unveiled the latest flagship high-performance vision/imaging DSP core. According to the company, the Cadence Tensilica Vision P5 digital signal processor (DSP) offers up to 13X performance boost, with an average of 5X less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP.

The Tensilica Vision P5 DSP is built from the ground up for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates. As such, it is geared for off-loading vision and imaging functions from the main CPU to increase throughput and reduce power. End-user applications that can benefit from the DSP's capabilities include image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction.

SuperGather technology

The Tensilica Vision P5 DSP core includes a significantly expanded and optimised instruction set architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems.

The advances in the Tensilica Vision P5 DSP further improve the ease of software development and porting, with comprehensive support for integer, fixed-point and floating-point data types and an advanced toolchain with a proven, auto-vectorising C compiler, detailed the company. The software environment also features complete support of standard OpenCV and OpenVX libraries for fast, high-level migration of existing imaging/vision applications with over 800 library functions.

The Tensilica Vision P5 core features a wide 1024bit memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing. In addition, it flaunts up to four vector ALU operations per cycle, each with up to 64-way data parallelism and up to five instructions issued per cycle from 128bit wide instruction delivering increased operation parallelism. The company also said the core boasts enhanced 8, 16 and 32bit ISA tuned for vision/imaging applications. An optional 16-way IEEE single-precision vector floating-point processing unit delivers a massive 32GFLOPs at 1GHz, added Cadence.

The Tensilica Vision P5 DSP is based on the Cadence Tensilica Xtensa architecture, and combines flexible hardware choices with a library of DSP functions and numerous vision/imaging applications from the company's established ecosystem partners. It also shares the comprehensive Tensilica partner ecosystem for other applications software, emulation and probes, silicon and services and much more.




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