Altera, Intrinsic-ID collaborate on secure high-end FPGAs14 Oct 2015
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Altera Corp. and Intrinsic-ID have teamed up to incorporate advanced security solutions into Altera's Stratix 10 FPGAs and SoCs. The integration of Intrinsic-ID's PUF technology within Stratix 10 FPGAs and SoCs boosts the security capabilities of the devices, addressing the growing need for security for all components used in systems, the companies stated.
PUF-based key storage is a new requirement for many defence and infrastructure applications to secure and bind software to hardware functions and prevent the cloning of systems.
Today's FPGAs and SoC FPGAs are sophisticated, multi-function components that demand the latest advancements in hardware security as a defence against greater adversarial challenges. Intrinsic-ID's PUF security solution adds strong anti-tamper protection to Stratix 10 FPGA-based systems by binding proprietary and sensitive design information to the unique physics of each individual device. Binding hardware functions and software to a PUF provides a very strong device authentication method and protection against cloning. The inclusion of PUF technology and the use of a secure device manager (SDM) for security management make Stratix 10 FPGAs and SoCs an ideal solution for use in military, cloud security and IoT infrastructure, where multi-layered security and partitioned IP protection are paramount.
The partnership between Altera and Intrinsic-ID enables users of Stratix 10 FPGAs and SoCs to license Intrinsic-ID's PUF technology for a variety of security use cases in their designs. Customer and user support will be enabled by Intrinsic-ID and by their support partner EndoSec for U.S. customers.
Serving as the central command centre for the entire FPGA, the SDM controls key operations such as configuration, device security, single event upset (SEU) responses and power management. The SDM creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoC devices, embedded hard IP blocks and I/O blocks.
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