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Single-ended die-to-die transceiver operates up to 20Gb/s

15 Oct 2015  | Gary Hilson

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As Dehlaghi and Chan Carusone outline in their paper, having the equalisation in the transmitter, decreases the amount of low frequency current being drawn from the transmitter power supply. This results in significant power savings. The passive equaliser also mitigates one of the main issues of single-ended signalling, which is power supply noise. Normally the power supply distribution network has a peak impedance around hundreds of MHz and drawing currents at those frequencies may result in a lot of power supply noise. By using a passive equaliser and shaping the transmitter current spectrum mostly to higher frequencies, the noise on the power supply is reduced.

For the transceiver/receiver design, an on-chip parallel PRBS7 generator is used to generate quarter-rate data in the transmitter. A half-rate differential clock signal is provided from off-chip and is divided into quadrature clock signals on-chip. The quarter rate PRBS7 signals are then serialised in a 4-to-1 multiplexer using the quadrature clock signals. The full-rate signal goes through a pre-driver and is delivered to the channel using the output driver.

The passive equaliser is programmable and can be bypassed using EQ BP switch. The receiver front-end comprises a termination impedance and a pre-amplifier stage that also extracts the reference signal from the incoming signal. Finally, the received signal is deserialised by a factor of four and sent off-chip.

In the experiment that Dehlaghi and Chan Carusone outlined in the research paper, a transceiver prototype was fabricated in 28nm with two identical transceiver dies flip-chip mounted onto a silicon interposer. The interposer chip included the interconnects between two dies as well as more decoupling capacitors for the power signals.

Ultimately, the researchers were able to demonstrate that he proposed transceiver can be used on both organic substrates and silicon interposers and consume 6.1mW at 20Gb/s over a 2.5mm interconnect with 10.7dB loss at Nyquist frequency and 4.8dB loss at DC. The energy efficiency of the proposed transceiver is mainly due to the use of CMOS building blocks, minimising current in the transmitter to receiver signal path, and lowering the signal swings on the channel.


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