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Grasp timing closure in multi-level partitioned SoCs

20 Oct 2015  | Syed Shakir Iqbal, Mitul Soni,Gourav Kapoor

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The only method for resolving such mismatches is to reduce the uncommon path across partitions and try to model it while accounting for all the type of uncertainties associated with it. However, as the levels of partitioning increase, both modeling and reduction of uncommon path can become a major challenge for the designer. In most cases, since the margin for uncommon path is generally on a bit pessimistic side, the minor pessimism associated through each level of partitioning tends to accumulate into a major chunk as we reach the lowest levels of partitions.

Figure 2 shows a typical example where the variation in the uncommon path across partition hierarchy can be seen easily. For the top level partition TOP_SOG, the uncommon path starts right after Z where are as going further into the hierarchy for APP_SUB_SYSTEM and APP_CORE the points are Y and X respectively. This implies that the effect of clock derates being applied at APP_CORE is much less as compared to TOP_SOG hence causing mismatch in timing which may result in a substantial increase in hold violations across the interface as well create noise variations as APP_CORE has a mismatch with APP_SUB_SYSTEM which itself has a mismatch with TOP_SOG.


Figure 2: Impact of uncommon and common path in multi-level hierarchical designs.


iii. Common path mismatch:

Earlier we discussed about the adverse effects of uncommon path in multi-level partitioned designs, however the common path associated with the external interface are of no less concern either , especially in case of noise analysis. A simple change in common path latency may pass on a small CPPR adjust in normal analysis, however, this change in delay may create overlaps in the timing windows which were earlier non-contributing; thus, degrading the noise profile and creating violations in even REG2REG internal paths which were met earlier with noise. Introducing more levels of partitions further increases the probability of such mismatches, thus creating doubts over the quality of block level design closure even after noise.

Consider the REG2REG path across REG E and REG F in APP_CORE as shown in figure 2. This is a completely internal path to APP_CORE but due to changes seen in the common path itself (till X) the variation of delay in arrival of clock edges when seen from TOP_SOG and APP_SUB_SYSTEM levels create a completely different timing window overlaps as shown in figure 3. Although these paths can be fixed by over optimizing them to model such mismatches but still during the design execution one can never be sure if the common path will remain untouched or not.


Figure 3: Impact of common path on SI (noise) timing window in multi-level hierarchical designs.


b) Physical Restrictions:

In multi-level partitioning as the number of physical partitions are increased so do the placement issues due to physical restrictions. Physical restrictions are generally reflected as either in limited port/pin/macro placement or modeling. The following are some of the key points that should be considered while dealing with physical challenges:

i. All the identical ports of both block and sub block should be placed nearby with minimum placement logic between them. These ports are commonly used to provide the connectivity for the TOP and sub block, hence min buffers should be used and placement should be handled very carefully.

ii. Placement of ports, macros and logic which are involved in loop back paths i.e. in2reg followed by reg2out or vice-versa should be driven by considering reasonable margins both in terms of timing as well as DRVs and DRCs as these are very likely to be bottlenecks in the later design stages.

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