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DMM copes with logic nanosecond-pulse-width waveforms

04 Nov 2015  | Marian Stofka

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When testing sequential-logic circuits, you may find that, although the repetition frequency of a logic signal is within the range of your digital multi-meter (DMM), you can't measure it. The displayed frequency value is either dubious or chaotically changing in time. The DMM may also behave as if there were no signal. Any of these undesired states might appear when the duty cycle of the measured waveform is either close to zero or is approaching one—in other words, when the width of a pulse—high or low—is much narrower than the repetition period of these pulses. This problem occurs because you can't expect a DMM with an upper frequency limit of perhaps 200kHz to measure 100-nsec-wide pulses, even if the repetition rate of these pulses is well below the upper limit of the DMM's frequency range—perhaps just 5kHz. For a rough estimation of bandwidth for measuring at a pulse width of 100 nsec, consider this pulse to be a half-period of a square-wave signal. Use the following equation to calculate the required bandwidth:



This frequency is well beyond the bandwidth of most DMMs. The second cause of failing to measure the repetition rate of logic waveforms with too-low or too-high duty cycles lies in the internal ac coupling of the DMMs during frequency measuring. Due to this coupling, the decision threshold of an internal comparator, which you derive from the mean value of the measured waveform, is close to either the low or the high level of this waveform. In the case of narrow pulses, the operation of the internal comparator becomes ambiguous, and any noise in the measured waveform or that the comparator itself generates may cause an error.


Figure 1: A binary divider turns low- or high-duty-cycle waveforms into square wave so that you can measure their frequencies.


You can address the problem by placing a binary divider between the source of a logic signal and the DMM. The binary divider comprises IC1, a positive-edge-triggered, D-type flip-flop (figure 1). The supply pin of IC1 connects to the supply terminal of the tested logic circuit. Therefore, you can run the logic at any industry-standard supply voltage of 1.2, 1.5, 1.8, or 2.5V. In testing 3.3V logic, use an external 2.5V source to supply IC1. The internal protective diodes at Pin 1 of IC1, along with resistor R1, reduce the voltage swing at Pin 1 to an acceptable level in such a case.


Figure 2: The flip-flop output, Q, produces a signal with a 50% duty cycle.


A square-wave signal is at the output of the binary divider (figure 2). The DMM no longer sees nanosecond pulses at its measuring terminal. You have only to multiply the displayed frequency value by two to obtain the correct frequency. Due to relatively low values of R1 and of the input capacitance, approximately 2.5 pF, at the clock input of the flip-flop, you need not worry about frequency compensation. The time constant of R1xCIN is merely 0.25 nsec. The width of pulses—either low or high—at the input of the circuit can decrease to 1 nsec.


About the author
Marián Štofka is with Slovak University of Technology in Bratislava, Slovakia.


This article is a Design Idea selected for re-publication by the editors. It was first published on August 20, 2009 in EDN.com.




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