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ARM brings enhancements to interconnect, memory control IP

29 Oct 2015  | Peter Clarke

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ARM has included additional features to its Corelink CCI coherent interconnect technology and digital memory controller, which according to the company serve as the basis for future heterogeneous system chips. The Corelink CCI-550 offers one to six ACE interfaces and one to six memory interfaces, as compared with the maximum four of each provided by the CCI-500. The Corelink supports "big-little" processing and connection to a fully coherent GPU while increasing peak throughput, indicated the company.

Corelink

The Corelink CCI-550 promises to provide up to a 60 per cent bandwidth increase as well as enhancements that reduce latency. An integrated and improved snoop filter function can save hundreds of milliwatts of power consumption, ARM said.

SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to six coherent processor clusters. The technology is suitable for a range of applications 4K resolution imaging in mobile and digital TV as well as automotive and networking applications.

CoreLink DMC-500, upgraded from DMC-400, offers support for LPDDR4/3 memory with enhanced quality-of-service for memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50GB/s for access to richer content such as 4K video for application in tablets and smartphones.

Acceleration through coherency

The improved support for GPU coherency in CoreLink CCI-550 enhances power management and delivers system-wide advantages. Coherency reduces development costs and time for new applications accelerated by heterogeneous processing for more efficient use of compute engines. OpenCL 2.0 with shared virtual memory features and other newer programming models take full advantage of system coherency. All processors work on the same data without unnecessary cache maintenance or memory copying. This also enables a system architecture fully aligned with the HSA coherency standards.

Scalable for multiple applications and higher throughput

CoreLink CCI-550 includes improvements in the microarchitecture to deliver higher peak throughput for demanding use cases and quality of service (QoS) enhancements that reduce latency by 20 per cent. SoC designers can configure the number of memory channels, tracker sizes, snoop filter capacity and scale up to six fully coherent processor clusters. The increased scalability addresses a range of applications beyond mobile including digital TV, automotive and cost-efficient networking applications noted the company.

More bandwidth, less latency

Time and energy-intensive memory transactions require a memory controller designed with a system approach to reduce bottlenecks. For ARM Cortex processors, CoreLink DMC-500 offers the lowest latency and power along with enhanced QoS for LPDDR4/3 memories operating up to LPDDR4-4267 transfer speeds. When integrated at the design level, CoreLink CCI-550 and CoreLink DMC-500 work together to deliver a peak system memory bandwidth beyond 50GB/s for access to richer content such as 4K video, ARM added.

Both CoreLink products have been delivered to lead partners and are available for licensing with production silicon expected by late 2016.




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