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Conducting thermal analysis of small outline packages

24 Nov 2015  | Robert Day

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With forced airflow, the junction-to-ambient thermal resistance could be further reduced, allowing higher powers to be dissipated and Tj to be kept under 150°C. The image below shows the package simulation in a forced-air environment. The following table shows the results for heatsink optimisation in forced air. It is interesting to see that, with forced airflow of 2m/s, the package could dissipate over 20W of heat for a fin height of 21mm and 17W with fins just 10mm high.

Package with heatsink in a forced-air environment

Package with heatsink in a forced-air environment

Thermal resistance versus fin height in forced air

Thermal resistance versus fin height in forced air. θja: junction-to-ambient thermal resistance, Pmax: maximum power

We did a similar parametric study for the smaller heatsink with a base of 30mm x 30mm for different fin heights in forced air. This smaller heatsink with 10mm high fins (lower weight) offered the same performance as a larger heatsink with 5mm fin height.

Thermal resistance and maximum power for forced air

Thermal resistance and maximum power for forced air. θja: junction-to-ambient thermal resistance, Pmax: maximum power

Several parameters effect the thermal conductivity of the board in the region of the vias. Creating a test board for every possible thermal via configuration and testing in a lab is practically infeasible. The CFD tool can be used to perform sensitivity studies of thermal performance to various via parameters, such as the pitch, plating thickness, and fill material. Such computational studies reduce the number of prototypes needed for testing or validation.

In a CFD programme, it is computationally intensive to model each and every via discretely, so we took a lumped approach where we replaced the region of vias with a block of orthotropic conductivity that had in-plane conductivity (kxy) and through-plane conductivity (kz). A board-import tool in the software was used to calculate the kxy and kz of this via block, but we could also have calculated these values analytically.

Thermal vias with an outer diameter of 0.3mm were studied. The image below shows the sensitivity of thermal conductivity of via block to pitch and plating thickness (t). The dielectric material used in this calculation was FR4 (k = 0.3W/mK), and the fill material was pure copper (k = 385W/mK).

Sensitivity to via pitch and plating thickness

Sensitivity to via pitch and plating thickness. kz: in-plane conductivity

Thermal simulations were conducted for PSOP in still air based on the conductivity values of the via cuboid. The results show that when plating thickness t is 75µm or higher, even sparsely populated vias are sufficient. However, at low plating thickness, say 25µm or lower, the vias need to be populated densely to ensure the component does not experience thermal failure.

Junction-to-ambient thermal resistance

Junction-to-ambient thermal resistance (θja) to via pitch and plating thickness in still air

Validating the simulation results

We conducted lab experiments to validate the CFD model results. The IC inside the PSOP package is capable of dissipating 10W and has an integrated temperature monitor. The relationship of the voltage at monitor-to-die temperature is not an absolute temperature indicator. However, the change in voltage verses temperature is a reliable indicator of relative changes in die temperature. Calibrating the temperature-monitor voltage verses temperature function was the first step in understanding die temperature used to determine thermal resistance.

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