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Design a 10-line-to-one-line data selector/multiplexer

03 Dec 2015  | Marian Stofka

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A 10-line-to-one-line data selector/multiplexer is typically required when dealing with logic operations over binary-coded-decimal (BCD) numbers. In the past, you could use the famous 16-line-to-one-line 74150 multiplexer IC. Nowadays, however, when you look at the Web sites of the renowned semiconductor houses for the 150 and similar 16-to-one multiplexers, such as the 250, the 850, or the 851, you find that vendors have labelled them obsolete or no longer available. On the other hand, the eight-line-to-one-line multiplexers not only have survived but also are parts of advanced logic families, such as high-speed CMOS (HC) and advanced CMOS (AC).

The circuit in the figure, a 10-line-to-one-line data selector/multiplexer, comprises two eight-to-one multiplexers, IC1 and IC2. The A, B, and C bits of the address input of IC1 connect to corresponding address bits—A, B, C, and D—of the main address input. The eight data inputs, D0 to D7, of the circuit are identical to the equally denoted data inputs of IC1.


Figure: The maximum worst-case propagation delay of this 10-line-to-one-line data selector/multiplexer is 27 nsec, whereas the typical value is only 6.8 nsec. The circuit can also serve as a 12-to-one multiplexer.


Whenever the main address is a binary-coded eight or nine, when A, B, C, and D=eight, the data input, D4 of IC2, is active. When A, B, C, and D=nine, D5 of IC2 is active. This shift in addressing of IC2's data inputs is due to the IC's modified addressing: Address bit C connects to the MSB (most-significant bit) D of the main address input. The A and B are common to IC1 and IC2, respectively. To unite their outputs without using any additional logic, you must connect the noninverting output, Y, of IC1 to data inputs D0 through D3 of IC2. The eight lowest values, zero through seven, of the address always activate a signal of D0 through D3 in IC2. The output signal of IC1 passes through one of these data inputs to the main output, Y2. If necessary, you can also use the W2 inverting output. Although the propagation delay from D0 through D7 to Y2 output is twice that from D8 and D9 to Y2, it is still less than 2×13.5 nsec=27 nsec for the CD74AC151 with a 5V supply. The typical delay is only 6.8 nsec.

Note that you can also use the circuit as a 12-line-to-one-line data selector/multiplexer by using the remaining data inputs, D6 and D7 of IC2, which are idle in this circuit. In such a case, you attribute another notation of D10 to the D6 input of IC2, and D11 holds for D7 one. Simultaneously, you must code the A, B, C, and D address in duodecimal code and, eventually, hexadecimal code, instead of BCD.


About the author
Marián Štofka is with the Slovak University of Technology in Bratislava, Slovakia.


This article is a Design Idea selected for re-publication by the editors. It was first published on June 11, 2009 in EDN.com.




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