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Will nanotube transistors gain traction in 2016?

02 Dec 2015  | R. Colin Johnson

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Japanese researcher Sumio Iijima at NEC (Japan) first discovered nanotube in 1991, describing it as the fourth form of carbon, after graphite, diamonds and fullerenes (Buckyballs). Nanotubes measure about 1.2nm in diameter (for the single walled variety). Essentially, they are atomically thin layers of graphene that are rolled into tubes.

Nanotubes were almost immediately identified as a possible replacement for the channel in silicon transistors, because their electron mobility is in excess of 100,000cm2/volt-second at room temperature—over 70 times faster than the 1,400cm2/Vs mobility of standard silicon chips.

Molybdenum disulfide

Postdoctoral fellow Wenzhuo Wu (left) and Professor Zhong Lin Wang (right) at Georgia Tech propose molybdenum disulfide as the wonder materials to replace silicon because it is extremely light, bendable, stretchable and piezoelectric. (Source: Rob Felt, Georgia Tech)

Different methods were tried to place pre-made nanotubes across the source and drain of a silicon transistors, and secondly to use a seed placed atop the source and drain and try to grow them in place. Such attempts have been made by labs around the world repeatedly from 2002 to 2015 but none have been as successful as placing pre-made nanotubes.

3D chip

3D chip from Stanford connects four layers with standard vias, with the bottom being standard CMOS, the top being carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM). (Source: Stanford University, Mitra/Wong Lab)

Nanotubes are easy to make by mechanical methods, but unfortunately some are metallic instead of semiconducting—due to their chirality—making it essential to find ways to eliminate the metallic kind which would just short-out a transistor. Two methods have been successfully developed, one sorting them ahead of time and the second burning out the metallic ones after placement with a high-voltage pulse, like opening a fuse.

Fabricated nanotube transistor

A diagram showing IBM's fabricated nanotube transistor with an end-bonded contact and a contact length below 10nm. (Source: IBM Research)

Once that problem was solved, the last problem became how to put them where you want them—as channels—on a silicon substrate. At first they were merely placed randomly, with little success, but in 2015 IBM reported a successful auto-alignment method for placing them across the source and drain, using as many of them as is necessary in parallel to carry the current needed.

TEM

Transmission electron microscope (TEM) Cross-sectional image showing the fabricated nanotube transistor with an end-bonded contact. (Source: IBM Research)


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