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Thermal analysis of small outline packages

08 Dec 2015  | Robert Day, Prasad Tota

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Across the electronics industry, sub-micron feature size at the die level is driving package component sizes down to the design-rule level of the early technologies. Today's integrated circuit (IC) package technology must deliver higher lead counts, reduced lead pitch, minimum footprint area, and significant reduced volume, which has led to semiconductor manufacturers developing the small outline package (SOP), surface-mount memory packaging.

SOP packages support the trend towards miniaturisation by consuming one-third to one-half the volume of earlier packaging alternatives. SOP components are a logical choice for the small form factor of handheld instruments, portable communication devices, laptop and notebook PCs, disc drives, and numerous other applications. The mechanical dimensions of the power SOP (PSOP) package, combined with a heat spreading thermal mass (copper slug), make it a good choice for office automation, industrial controls, networking, and consumer applications that generate internal heat and are exposed to stressful temperature conditions.

The PSOP leads are located on the long side of the package, which leaves two sides of the package open. The open sides of the package can be used to route traces under the component, conserving board layers and simplifying board layout. Compared to older versions, the packages can be placed much closer to each other and to other components on the board.

When IC packages are downsized, thermal power density increases, and the heat-transfer path from the die to the external ambient needs to be optimised to allow for maximum possible power dissipation at the die while still ensuring the die temperature is under the maximum allowable value. Although PSOPs undergo tests for reliability under temperature stresses, electrical flow, and solderability, as well as mechanical inspection at the manufacturer before shipping, it would be time-consuming and expensive to physically test or design test boards to test a package in all its possible applications and configurations.

Computational fluid dynamics (CFD) software is useful in such situations because it can simulate and estimate the junction temperature (Tj) of the IC when attached to the PCB under various conditions, including different powering conditions, board conductivity, thermal via distribution, bill of materials, and the IC package construction itself. A CFD tool enables a mechanical or electrical engineer and/or IC designer to quickly see the effect of design changes from a thermal management perspective both qualitatively and quantitatively.

To test this, we performed computational thermal analysis of an Analog Devices high-speed, high-voltage, 1-A output drive amplifier, the ADA4870-1, PSOP mounted on a PCB,[1] using Mentor Graphic's CFD FloTHERM. Specifically, we wanted to identify the maximum power that could be dissipated on the die active area while keeping the Tj at less than 150°C. We studied various environments to estimate this maximum power, for example, changing the board area, adding thermal vias, and attaching a heatsink.

This package can be surface-mounted on the board either slug down or slug up (figure 1), depending on the direction of the formed leads. In a slug-down configuration, the component is surface-mounted on the primary side of the board where the copper slug is soldered to the top side of the board. In a slug-up configuration, the leads are soldered to the primary side of the board. For our experiment, we used a slug-down configuration; first with no heatsink, and then with a heatsink attached to the secondary side of the board with thermal grease between the board and the heatsink base.

Figure 1: The PSOP dimensions in millimeters, with the copper slug on the bottom.

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