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Grasp interconnect verification in SoC design (Part 2)

14 Dec 2015  | Ramneek Real, Janak Patel, Bhavin Patel

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Error detection, logging, forwarding and recovery
The typical interconnect can provide mechanisms for error detection and logging to avoid dead-lock situations in the system. Interconnect provides

 • Identification of error source and error type
 • Mechanism to recover from erroneous state to normal operation mode.

This mechanism can be adjusted to match the needs of the system. In general, four different types of errors can be detected by the interconnect:

1. In-band / Out-of-band error reporting: When any slave gives response error through its response channel

2. Secured / Non-secured access control: While using protection mechanism

3. Illegal access control: By targeting reserve space or generating invalid command i.e. write command to ROM

Transaction timeout: When any slave is in reset while receiving the transaction or it stops servicing the requests (e.g. by back pressure from slave, clock/ power gating)

Figure 2: Error Reporting and Forwarding.


As error reporting and detection is essential part of interconnect, it is required to check all afore-mentioned errors with reporting and forwarding enabled and disabled configurations. To check each type of error, it is important to generate special traffic patterns from different initiators.

In any of the cases, interconnect should not go into deadlock. It is also preferred to check normal operations before and after error injection with software recovery flow. To come out of the error state and commence on normal operations, the application software may have to follow some predefined dedicated recovery flow. This recovery flow should be thoroughly verified with multiple error injections on different parts of interconnect at the same time with reporting and forwarding enabled. To make sure that different types of error reporting and forwarding for each target and initiator is checked, we implemented functional coverage for error reporting checking that showed coverage for errors checked at each initiator and target.


Request arbitration and buffering
Interconnect designs have multiple arbitrations and buffering at different junctions which solely impact system performance. Hence in interconnect, this feature shall be verified by targeting performance verification to match system performance criteria.


About the authors
Janak Patel & Bhavin Patel are with eInfochips.

Ramneek Real is with Toshiba.


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