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Understand slope compensation in PCMC DC-DC converters

16 Dec 2015  | Sergio Franco

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Central to the system is the error amplifier EA, a high-gain amplifier that compares ?VO against a reference voltage VREF and outputs whatever voltage vEA it takes to make their difference approach zero, thus giving



Once it reaches its steady state, the circuit operates as follows:

A cycle initiates when a clock pulse sets the flip-flop. This closes the Mp switch to make vSW = VI. During this portion of the cycle, denoted as DTS in figure 4, the inductor current iL ramps up with a slope of Sn governed by the iL-vL inductor law, or Sn = diL/dt = vL/L. During this time we have vL = VIVO, so




Figure 4: Steady-state waveforms in peak-current-mode control (PCMC).


Turning back to figure 3, we observe that the CMP comparator continuously compares the voltage RiiL against the voltage vEA, and that as soon as RiiL reaches vEA, the CMP trips to reset the flip-flop. Dividing both sides by Ri, this is equivalent to saying that the CMP trips as soon as iL reaches the value



This allows us to visualise a cycleexclusively in terms of currents as in figure 4. Now, resetting the flip-flop opens the Mp switch while closing the Mn switch to make vSW = 0. During the remainder of the cycle, denoted as (1 – D)TS, we have vL = 0 – VO, so iL ramps down with a slope of Sf such that



A new cycle begins with the arrival of the next clock pulse.


Two flaws of uncompensated PCMC
As is, the circuit of figure 3 suffers from two flaws. The first flaw is depicted in figure 5 for the case of a


Figure 5: The inductor current of the circuit of Figure 3 for two different duty cycles.


converter designed to regulate VO at 3.0 V (for simplicity, a cycle is assumed to start at t = 0). Figure 4a shows the steady-state inductor current iL and its average IL for the case VI = 9 V, corresponding to a duty cycle of D = 3/9 = 1/3. Suppose now VI drops to 4.5 V, corresponding to a duty cycle of D = 3/4.5 = 2/3. Assuming vEA hasn't had time to change appreciably, the average inductor current IL will rise as in figure 5b. This is so because while the down-slope Sf remains constant at –3/L, the up-slope Sn decreases from (9 – 3)/L to (4.5 – 3)/L, that is, from 6/L to 1.5/L. With an increased IL, VO will also tend to increase, indicating poor regulation.

The second flaw is a form of instability known as sub-harmonic oscillation, which arises for D > 0.5. Figure 6 shows how an inductor current perturbation il(0) at the beginning of a cycle evolves into the perturbation il(TS) at the end of the cycle. (A perturbation might be due, for instance, to a misfiring of the comparator in the course of the previous cycle.) Using simple geometry we can write il(0)/Δt = Sn and il(TS)/Δt = Sf. Eliminating Δt gives




Figure 6: Illustrating sub-harmonic oscillation for D > 0.5.


indicating that (a) the polarity of il(TS) is opposite to that of il(0), and (b) for D < 0.5 its magnitude will decrease to die out after a sufficient number of cycles, but for D > 0.5 it will tend to increase from one cycle to the next, leading to the aforementioned sub-harmonic instability.

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