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RISC-V welcomes Google, HP, Oracle

29 Dec 2015  | Rick Merritt

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At the workshop, two talks will describe boot environments for RISC-V in separate papers presented by engineers from Google and a team from HPE and Intel. A representative of military contractor BAE Systems will talk about building the software ecosystem for RISC-V.

FPGA accelerators tap RISC-V

Three papers will describe FPGA-based accelerators using embedded RISC-V cores, a hot area given work by Web giants such as Microsoft and Baidu on FPGA accelerators.

Jan Gray, a former software architect on a Microsoft parallel computer, will describe an FPGA accelerator using RISC-V cores. Guy Lemieux, an academic and CEO of VectorBlox Computing, will describe a similar project.

ROA Logic, an FPGA and ASIC design services company in the Netherlands, will describe various RISC-V implementations.

"I was surprised by how many people are getting involved. We'll be sold out with about 130 people," said O'Connor. "You'll see folks developing products that cover the waterfront from embedded to high-end server-class processors, initial [commercial] products will be lower-end embedded SoCs," he added.

The RISC-V instruction set supports 32 and 64bit designs as well as vector and out-of-order extensions.

Even if it gains significant traction, RISC-V is not likely to have any major impact on ARM and Mips, given those vendors are well established with broad sets of customers and partners. However, the architecture could enable a new class of designs from small teams that would otherwise lack the heft to design their own chips.

Smaller, lower cost alternatives to ARM such as Andes, a startup core designer in Taiwan, might be the most likely to lose design wins to the open source architecture.


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