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Sample-and-hold amplifier holds difference of two inputs

01 Mar 2016  | Marian Stofka

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You can satisfy a requirement for sampling the difference of two signals in two classic ways. You can subtract the two input signals with an instrumentation amplifier whose output connects to an input of a classic sample-and-hold amplifier. Despite the positive feature of needing no external resistors for a gain-of-one differencing instrumentation amplifier, this approach suffers from high relative output distortion when the inputs are of the same polarity and close in magnitude. In such a case, the difference of two input signals is close to 0V, and the amplifier is therefore more vulnerable to residual dynamic imperfections of the sample-and-hold amp. The other approach is to separately sample the two input voltages in two sample-and-hold amps and subtract the outputs of these amps in an instrumentation amp. Here, the relative error of output signal with similar input waveforms is lower than in the first approach.


Figure 1: The basis for the operation of this circuit is the simultaneous tracking of the VINA and VINB input voltages on capacitors C1 and C2 and a stacking of these capacitors within the sample interval on capacitor C3.


If you like all-in-one solutions, you can use the circuit configuration in figure 1. This circuit simultaneously tracks both input voltages, VINA and VINB, at an active-high level of the internal logic-control signal, which enables the A1, B1, and A2 voltage followers. VINA thus appears on capacitor C2, which is ground-referenced. Capacitor C1, which is temporarily grounded at its upper node, Pin 9 of IC1, tracks the VINB voltage. After a settling interval when all of the internal logic-control signals go inactive low, the QSB logic-control signal goes high. The voltage of VC2(TS)=VINA(TS) shifts the potential at the lower node of capacitor C1 because of the enabled B3 follower. Upon the sample command, QS is high, and the upper node of C1 is grounded within the tracking interval. Storage capacitor C3 therefore charges through the B2 follower to a voltage of VC2(TS)–VC1(TS)=VINA(TS)–VINB(TS). The A3 follower serves as an impedance converter.

The voltage gains of both the A and the B channels are slightly lower than ideal. This slight gain decrease has approximately the same value for both channels: δGAINAGAINB~(COUTB1/C1). The equality of gain decrements on both channels stems from the fact that the upper node of the storage capacitor, C1, connects at the instant that QSB goes high to the output capacitor, COUTB1, of the disabled follower, B1. Follower B1 always discharges to 0V within the tracking interval without regard to the voltages at the A and B inputs. For Analog Devices' AD8592 op amps, the output capacitance, COUT, in the disabled state is approximately 26.2 pF.

Note, however, that if VINA and VINB are of opposite polarity and of equal magnitude, almost reaching the value of VS/2, the output voltage approaches either the positive- or the negative-supply rail. In this case, the relative output error is about twice that given in the previous equation. The op amps' capacitance rises as the output voltage approaches any of the supply rails, reaching the value of 55 pF. This increasing output capacitance arises from one of the complementary power transistors in the AD8592's output stage as its drain-to-source voltage approaches 0V at the output voltage close to the positive-supply rail. The increasing drain-to-source capacitance with decreasing drain-to-source voltage is an inherent property of MOSFET transistors. The same situation holds true for the bottom power transistor of the AD8592's output stage, when the output voltage approaches the negative-supply rail.

The turn-on time of the AD8592 is much longer than the turn-off time. Although the device's data sheet does not directly specify these times, you can see from the internal structure of the IC that the on/off control enters almost all of the IC's stages (Reference 1). Thus, turn-off is fast because the turn-off of the output stage occurs without regard for the states of the preceding stages. Within one period of operation of the circuit in figure 1, a sequence of two turn-ons (TON) plus four intentionally added delays (TDE) determines the shortest sampling period: TMIN~TONB3+4TDE+TONA1B1A2. Here, TONA1B1A2 is the largest from among the values of turn-on times of followers A1, B1, and A2, which depend on the actual values of VINA and VINB. The maximum sampling frequency is then 1/2(TON+2TDE).

If you assume that the maximum turn-on time can reach the value of the over-voltage-recovery time of approximately 3µsec and that the delay time is approximately 0.35µsec, then it follows that the maximum sampling frequency is approximately 135kHz. The duty-factor of the external logic-control signal, Q, for sampling frequencies near the value of the maximum sampling frequency should be about 0.5.


Reference
"AD8592-Dual, CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifier," Analog Devices Inc, 1999.


About the author
Marián Stofka is with Slovak University of Technology in Bratislava, Slovakia.


This article is a Design Idea selected for re-publication by the editors. It was first published on August 7, 2008 in EDN.com.




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