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Dealing with switch-node ringing in DC/DC converters

29 Feb 2016  | Vijay Choudhary

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Unlike the spikes on the high side (as shown in the buck converter example in figure 3), you cannot easily circumvent negative switch-node ringing issues by selecting a FET or controller with a higher voltage rating, because a higher-voltage-rated IC does not necessarily have higher margin on the driver circuit or a more negative switch-node rating.

Although you can apply some of the techniques in dealing with buck switch-node ringing to boost switch-node ringing, others you cannot.


Methods of protecting against boost switch-node ringing

Gate resistors
Gate resistors (figure 6) can effectively reduce the drive strength of the driver and slow down the turn on of the control FET. A slower transition on the switch node results in lower voltage spikes and lower ringing on the SW2 node. figure 7 shows the reduced ringing in the presence of a gate resistor.

The use of gate resistors is not without pitfalls. First, the slowing down of the switching event causes extra switching losses. Second, the gate resistor can delay turn off of the control MOSFET and increase the risk of cross-conduction between the high (synchronous)- and low (control)-side FETs. To avoid delay in the control MOSFET turn off, a diode is often necessary, in parallel with the resistor, for fast pull down (figure 6).


figure 6: Gate resistor (with a diode pull down) and snubbers can slow down the turn on of QL2 and reduce the negative spike/ringing.


figure 7: G A gate resistor in a boost-control FET reduces the ringing on SW2.


Snubbers
Snubbers (figure 6) can reduce the peak of the ringing as well as damp it. Snubbers work by damping the LC tank formed by the parasitic inductance in the switching current loop and the output capacitance of the MOSFET. figure 8 shows a reduction in switch-node spikes as well the number of excursions due to a properly designed snubber. Reference [2] describes the selection of RC snubbers for nonisolated converters.


figure 8: Reducing SW2 node negative spikes and ringing using a well-selected snubber.


FET selection
Different MOSFET parameters can have significant impact on the frequency and peak of switch-node ringing.

The MOSFET parameters responsible for ringing are the reverse-recovery charge of the body diode and the output capacitance, COSS. In addition, the gate charge of the MOSFET determines the turn-on or turn-off times of the MOSFET. A lower Qg means a faster turn off, which results in larger spikes.


Layout
The power-stage layout is one of the most important elements of a good switching-converter design. Since parasitic inductance of the switching current loop contributes to the ringing, its minimisation is always the primary goal of DC/DC converter layout. In figure 9, the loop area of MOSFETs QL2 and QH2, bypass capacitors COUT, and sense resistor RSENSE form the switching current path. You should make this loop (shown in green in figure 9) as small as possible, with thick traces on multiple layers connecting the elements of the loop. figure 9 shows an example layout of a buck-boost power stage, with the high di/dt loops in buck and boost power stages highlighted.

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