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Next-gen RTL synthesis improves design speed predictability

10 Mar 2016  | Arvind Narayanan

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A side benefit of having high-quality physical RTL output is that it makes the entire design flow more predictable with shorter design cycles. Optimising at a higher level reduces RTL synthesis runtime, gives faster design convergence and cuts the time-consuming iterations. Using a high-level RTL physical synthesis solution with the capacity to handle 100+ million gate designs will deliver an enormous increase in productivity.

The third barrier to QoR is the general lack of robust what-if analysis during RTL synthesis. With a newer-generation RTL synthesis tool, designers can cross-probe between physical and RTL databases to debug timing or congestion problems. They can also perform parallel explorations of different design metrics, for example, varying the weight of power, performance, timing, DFT, and area to find the best alternative for implementation. The tool should be able to perform multiple fast synthesis runs with the different constraints for voltage, clock speed, and library, and gives the results in a comprehensive summary format.

scan chains

Figure 2: Fast design-space exploration enables the designer to check and modify the design to meet timing, power, area, congestion, and DFT specifications.

A final thought on design quality is the importance of chip-level DFT. Testability is increasingly difficult and undeniably important. Selecting DFT friendly architectures early and performing scan insertion at the full-chip RTL level helps reduce test time and limits the impact of test logic on die size. Physical RTL synthesis takes into account the physical location of flops when creating scan chains. Working at the chip level is better than working at the block level and then manually hooking up the sub-chains. Performing scan insertion during synthesis also lets potential test problems be debugged early in the design cycle.

scan chains

Figure 3: The screen shot on the left shows a design in which the scan chains have not been ordered with their physical placement taken into account. The screen shot on the right shows the same design re-implemented using the physical placement information. Each scan chain is a different colour so the advantage in terms of routing is clear.

Good RTL synthesis is critical for improving the performance, power, and area challenges in today's large advanced-node SoCs. A next-generation physical RTL synthesis tool must have higher capacity, faster runtimes, and better QoR than what's available in traditional synthesis solutions.


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