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On-chip PVT monitoring to streamline shrinking SoC design

21 Apr 2016  | Ramsay Allen

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Oliver King, Moortec's CTO, has been spearheading the development of compelling on-chip monitoring solutions to tackle problems associated with ever-shrinking SoC geometries. King is now leading the expansion of the company's IP portfolio into new products on advanced nodes. He has also share his views on the need for accurate process, voltage, and temperature (PVT) on-chip monitoring.

Why is there an increasing requirement for monitoring on chip?

Since the beginning of the semiconductor industry, we have relied on a doubling of transistor count per unit area every 18 months as a way to increase performance and functionality of devices. Since 28nm, this has broken. As such, designers now need to find new ways to continue increasing performance.

Using the analogy of the internal combustion engine, for decades it was fine to have the fuel consumption and emissions that they had as the innovation was limited. Improvements to cars focused around adding features, adding things which made the car a nicer place to be. People bought new cars because they wanted the latest features. Then oil prices started going up, we became aware of the environmental impact, and with this innovation aimed at improving the efficiency of the engine. The result is quite astounding, the modern car engine delivers more power whilst consuming less fuel and emitting less harmful gasses.

Oliver King

King: On-chip PVT monitoring is here to stay.

The semiconductor industry is now in the position where it has to do the same. We can no longer rely on adding more transistors to make a better, faster, chip. The customer still wants their new computer, phone, or tablet, to be faster and have more storage than their old one.

One technique being deployed to provide the improvement is device optimisation. By being aware of a devices thermal and voltage environment and understanding where a given device is within the ever increasing sphere of device variation, allows the system architects and circuit designers to get more from a given piece of silicon. With the increase as well in the cost of advanced nodes, this is becoming even more important to ensure every last drop of performance is extracted from a die.

Is this just an issue for the advanced nodes?

In short, no. With the growth in the IoT market, we are going to see an explosion in the number of wireless devices. A majority of these will be on older process nodes, however, the same performance gains can be found on these nodes. These devices will typically be battery powered and sensitive to power consumption. Because of this there will be a drive to improve efficiency in these products rather than perhaps improving performance, but they are different names for essentially the same problem. By understanding where a given die is with respect to process, voltage, and temperature, a more optimum solution can be found, whether that optimum solution is measured by performance or efficiency doesn't matter.

Then we also have to consider automotive, which is a big growth area for the semiconductor industry as a whole. With the growth of the advanced driver assistance systems (ADAS) and Infotainment areas we will see more advanced nodes being used, certainly down to 28nm in the near future. Ideally some of these products would be on more advanced nodes but those are not qualified for automotive.

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