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Logic simulator silos aim to cut verification debug time

28 Apr 2016

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CM Engineering Co. Ltd and Silvaco Japan Co. Ltd have revealed that the SpecInsight family of products provided by CM Engineering now supports Silvaco's logic simulator Silos.

The SpecInsight family product SpecInsight-TEX provided by CM Engineering supports Silvaco's Verilog logic simulator Silos, thereby making it possible to automatically generate execution scripts for Silos and test benches that can be simulated with Silos. By adding a function to link Silos with SpecInsight-TEX, which automatically generates test benches and verification scenarios, from timing charts created for specifications, the user receives the a number of benefits.

Firstly, the function for automatically generating verification data from a SpecInsight-TEX timing chart and Silos' exceptional debugging functionality make it possible to reduce by 50 per cent or more the TAT from verification environment construction through confirmation of simulation results, thus greatly contributing to a reduction in LSI/FPGA development times.

SpecInsight-TEX

Figure 1: SpecInsight family product SpecInsight-TEX provided by CM Engineering supports Silvaco's Verilog logic simulator Silos

Secondly, the output of test benches generated by SpecInsight-TEX can be automatically checked. Combining this with the syntax check function and code coverage function of Silos makes it possible to perform high quality design in a short period of time, and thus contributes to both reducing costs and improving the design quality of the final product for customers.




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