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32bit microcontroller IP core designed for high-performance ASICs

05 Jun 2012

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Cortus has launched the latest member of its processor family, the APS5, which the company describes as its high-performance, high-throughput 32bit processor designed for complex embedded systems. The APS5 combines good integer computational performance with a high maximum clock frequency. This processor IP is designed for ASICs requiring more complex processor subsystems, such as those with instruction and data caches or co-processors. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.

The Cortus APS5 with a high-performance integer unit and an instruction cache is the third member of the Cortus microcontroller IP core family to be released this year. It complements the smaller-energy-efficient APS3R and the larger-floating-point FPS6.

Says Michael Chapman, CEO and president of Cortus: "Despite its modest CPU core area, the APS5 delivers 2.29 DMIPS/MHz". In common with other Cortus processors, the APS5 has a 5- to 7-stage integer pipeline and out-of-order completion. This ensures that most integer instructions (load and stores included) are executed in a single cycle. Chapman explains: "The APS5 architecture enables a high maximum clock frequency ... capable of greater than 400MHz in a 90 nm technology".

The APS5 has also been designed to provide scalable computing performance and is supplied with an instruction cache and an optional data cache. Performance can be increased with symmetric multiprocessing (SMP) configurations, such as dual- or quad-core. For instance, while a single APS5 core offers 1.93 CoreMarks/MHz, a dual-core configuration benchmarks at 3.51 CoreMarks/MHz. For SMP configurations, a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations.

The modest APS5 CPU core silicon footprint of 0.088 mm2 in 90 nm (UMC) and the freely-available complete toolchain and IDE ensure a low cost of ownership for APS5 licensees. Easy software development, programming in high-level languages, with simple debugging due to an integrated debugger and simulator, all enhance both time-to-market and software reliability.

As a member of the Cortus family of processors, APS5 interfaces to all of Cortus' peripherals. These include Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure, which ensures rapid, real-time interrupt response, with low software overhead. Bridges to and from AHB-Lite and to APB ensure easy interfacing to other IP.

The APS toolchain and IDE (for C and C++) is available to licensees free of charge and can be customized and branded for final customer use. Ports of various RTOSs, such as FreeRTOS, MicriumµC/OS andµCLinux, are available.

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