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Address timing miscorrelation using timing uncertainties

16 Aug 2012  | Ateet Mishra, Jatinder Kumar, Uchit Singhal

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With rapidly developing technology, the complexity of VLSI designs is increasing day by day. The new flows and checks are introduced to ensure a good yield of working silicon. The complete flow includes the usage of multiple EDA tools (e.g., Encounter, ICC, Magma, Talus, ETS, Prime Time, etc). Optimization could be the strength of one tool while for timing sign-off we need another. With this the correlation among different tools has become a challenge. Timing is one of the very important aspects of design closure. Timing correlation between the implementation tool and the timing sign-off tool has become a big concern. Our paper discusses this timing correlation issue and proposes a workable solution.

There are so many variables involved in the timing analysis. Every variable has a different tendency to vary with design condition. Sometimes implementation tools, to reduce the runtime of implementations, do some approximations in computation. Design net RC extraction and delay calculation algorithm are two such examples. This results in miscorrelation between the timing sign-off tool and the implementation tool. For a perfect design closure, it is very important that the implementation tool sees the exact result as required by the timing sign-off tool.

Let's take an example to explain the above mentioned correlation issue. Let Tool A be the optimization tool and Tool B the timing sign-off tool. Following figure has considered all possible scenarios that can arise out of the miscorrelation.

Let's consider the following list of top violating and critical paths and their timing slack in both the tools. If we observe the difference in timing slack, there might not be any definite pattern in slack difference (Delta). The timing difference can't be modeled as a flat timing derate or flat uncertainty. In other words, the miscorrelation on each timing path is non deterministic.

Miscorrelation impact in NPI execution cycle:

Due to this miscorrelation, the optimization tool will keep on optimizing the timing violations which are not real and will leave the violations that need to be fixed. This in turn will lead to:

 • Extra pessimistic closure, which leads to increase in silicon area.
 • Leaving number of unfixed violations.
 • Manual iteration with huge turnaround time of design closure.

Proposed strategy
A resolution of the above explained problem is to make the actual scenario visible to the optimization tool. We need to match the slack of the violating paths and the top critical paths (with marginal positive slack) between the sign-off tool and the optimization tool. We have played with the individual clock uncertainty of such paths and enabled the optimization tool to see exactly same timing profiles as that of sign-off tool. In our example, we have assumed the original uncertainty in both the tools to be 50ps. But now the new uncertainty for Tool A will be the difference of Delta and the original uncertainty. On applying this new uncertainty in Tool A, the number and magnitude of violations in both tools (Tool A and Tool B) will match. This will help avoid extra-pessimistic closure with less manual iteration. This has also been illustrated in the table below.


The suggested strategy solves the miscorrelation problem between the timing and the optimization tools in a way that helps avoid extra pessimism in the design, thus saving on area and power.

About the authors
Ateet Mishra is a staff design engineer at Freescale Semiconductor, India. He has seven years of industry experience in various fields of VLSI, such as static timing analysis and physical implementation and synthesis. Mishra has been associated with Freescale since the beginning of his career and has successfully taped out multiple SOCs in various technologies ranging from 250 to 40 nm.

Jatinder Kumar is a design engineer at Freescale Semiconductor, India. He has two and a half years of industry experience in physical design and is a physical implementation expert. Kumar takes care of design flow from placement until complete SI closure and has successfully taped out multiple SOCs in various technologies ranging from 90 to 40 nm.

Uchit Singhal is a design engineer at Freescale Semiconductor, India. He has two and a half years of industry experience in physical design. Singhal is a static timing analysis expert and has successfully taped out multiple SOCs in various technologies ranging from 90 to 40 nm with multiple partitions.

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