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Employ analog behavioral models for mixed-signal SOC verification

30 Aug 2012  | Qi Wang

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The creation of analog behavioral models can be challenging. Analog designers are in the best position to create such models because they are familiar with their own circuits. Many analog designers lack the programming skills and knowledge required to construct behavioral models, however, and few are familiar with Verilog or VHDL. Digital designers, conversely, have expertise with behavioral models but know less about analog circuits.

That dichotomy creates an opportunity for tool vendors to offer an automated or semi-automated solution for generating analog behavioral models. For example, automated, netlist-driven model-generation technologies can create a fairly accurate parametric behavioral model that considers PVT (process, voltage, and temperature) and loading variations for functional verification. Such an approach has shown some limited success on a subset of analog-circuit architectures under specific contexts, but there is still much work to be done to develop a general model-generation methodology with high accuracy that can be applied to any analog or mixed-signal design.

Creating behavioral models is only one part of the process of using those models in a mixed-signal verification flow. If the model and implementation do not match, the effort is worthless; worse, it can damage the entire design process. As a result, there is a need for a methodology to validate the accuracy of a behavioral model automatically against the corresponding design. The model also must be updated to keep it in sync with any changes made in the implementation.

The model-validation flow shown in figure 2 simulates the implementation and behavioral models using the same test bench, with the relevant tools and flows creating the required measured-results behavior and waveform for each model. The designer can use the flow to validate that:

 • The implementation- and behavioral-model measured results are within user-provided tolerances;
 • The implementation- and behavioral-model waveforms are within user-provided tolerances; and
 • Selected elements of the interfaces and pins of the behavioral and implementation models match.
This approach provides a self-contained, automated analog-behavioral-model verification and debugging environment. The method lets users provide verification requirements through interactive configuration, and it uses the existing mixed-signal simulation setup to validate both the waveform signals and the measured results. Interactive verification-failure debug lets designers quickly identify problems in a model and rerun validation after fixing them.

That is just the beginning of the advantages that can be brought into the analog-verification world. The digital domain has many other tools at its disposal—such as verification planning, coverage, and assertions—that can apply to analog verification given the right language extensions.

Assertions' role
Assertions capture aspects of a specification and design intent in an executable form. They act as monitors during simulation, detecting errors close to their source and reporting both errors and coverage information. Through the use of assertions, verification can start earlier; design and verification teams can detect and remove bugs faster; and designers can incorporate their intent into the design code, thereby minimizing integration issues later on. The mixed-signal design and verification communities embracing ABV methodologies can reap the benefits of assertions and tools in the following ways:

 • Assertions capture design intent and can be incorporated with the design;
 • Assertions detect errors closer to their source, speeding removal; and
 • Assertions provide control-oriented functional coverage information.

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