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IJTAG standard defined

28 Aug 2012

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A new introductory tutorial from ASSET InterTech explains how the new IEEE P1687 Internal JTAG (IJTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization.

The IJTAG standard, which is expected to be voted on later this year via the IEEE's normal standards process, specifies a standard interface to instruments embedded in chips and defines a methodology for accessing them, automating their operations and analyzing their outputs.

To allow for a wide variety of functionality, an instrument's core intellectual property (IP) does not need to conform to the IJTAG standard, just the instrument's interface to the on-chip IJTAG network. With standardized embedded instrumentation chip designers are better able to manage the hundreds or thousands of instruments that are typically embedded in complex components and systems-on-a-chip. The standard defines an architecture that can automatically connect all IJTAG instruments as well as an access methodology for automating their operations.

The IJTAG standard simplifies and accelerates the chip designer's job when it comes to validating and debugging chips. Later in the life cycle, those same embedded instruments can be re-used by board-level manufacturers to validate, test and debug circuit boards. IJTAG reduces time-to-market, streamlines part of the design process and cuts test costs for both chip vendors and board manufacturers.

Asset's IJTAG Tutorial describes the on-chip IJTAG architecture as well as the two languages defined by the standard, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded on-chip instruments and PDL is an extension of the popular Tcl (Tool Command Language) for developing validation, test and debug vectors for execution by IJTAG instruments.

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