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EZchip unveils Network Processor for Smart networks

07 Sep 2012

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EZchip Semiconductor unveiled what it describes as a revolutionary network processor (NPU) that will enable the next generation of smart high-performance carrier and data-center equipment. According to the company, the Network Processor for Smart networks (NPS) boosts the flexibility and performance of traditional NPUs and CPUs to enable advanced baseline features for carrier equipment and to scale the performance levels of data-center equipment.

Through its breakthrough architecture, NPS breaks the barriers imposed by traditional NPUs and CPUs. It enables extremely high-performance C-programmable layer 2-7 processing, and provides networking vendors with an architecture that scales as more advanced services at higher speeds are required over time, noted EZchip.

For carrier equipment, the NPS enables the migration of advanced layer 4-7 features from specialized services cards to common line cards and enables the line card with new baseline features such as application recognition and IPSec VPNs, as well as greater velocity for adding new features. For data-center equipment, the NPS allows scaling their performance to the required loads of the evolving data center for greater layer 2-7 capabilities within constrained power and space. It empowers data-center appliances as well as carrier appliances with line-rate performance for applications such as load balancing, firewall and OpenFlow/SDN and network virtualization.

The NPS is geared for data-plane processing where packet processing and wire-speed forwarding prevail, unlike CPUs that are designed for general processing where management functions and control-plane processing prevail. Central to the NPS are its innovative C-programmable task optimized processors. These processing engines build on EZchip's extensive NPU experience and are designed specifically for data-plane processing. The optimized design allows the integration of 256 such processors, each with 16 threads, for a total of 4K virtual processing engines. This vast number of engines is mandatory for high-speed data-plane processing where packets are arriving at an extremely high rate and every packet is processed. The NPS architecture is in contrast to CPUs that have an order of magnitude fewer engines integrated into a chip because they are based on much larger general-purpose cores, have large memory caches, designed to execute millions lines of code, and target both data and control processing. The NPS' efficient design allows incorporating into the chip not only a great number of cores but also EZchip's market-proven hardware traffic manager, a task optimized memory architecture, and numerous hardware accelerators for efficient table lookups, application recognition and security. The end result is a very powerful network processor with superior power efficiency and integration, detailed the company.

EZchip will deliver the NPS-400 and NPS-200 products with 400Gb and 200Gb throughput, respectively. Samples are planned for 4Q13 and other derivative products will follow. EZchip customers for the NP-2/3/4/5 products will have the option to maintain the benefits of code portability and scale up with a future NP-6, or C-program their applications and benefit from the new capabilities of the NPS.

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