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Basics of solid-state memory technologies in consumer electronics (Part 2)

03 Oct 2012  | Thomas Coughlin

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Somewhat similarly, writing into these chips is a bit more daunting than writing into SLC chips. Across the chip, different cells behave differently, and relatively sophisticated state machines (tiny little computers) are used first to put a smidgen of charge onto a floating gate, next to measure to see if the floating gate's charge is near the optimum charge for the cell to represent one of the four levels, then to continue iterating this process until it is done. Usually, a smaller current is used to give better control over the charge, and this slows down programming. Precision takes time.

This is a good idea. Why not take it to the next level to store more than two bits on a cell? This is precisely what several companies have tried to do for a number of years, but there are many problems that have proven tough to overcome. The biggest one is that the fractional voltages, as they get smaller and smaller, become increasingly difficult to pull out of the noise inherent on a digital chip. Another is a mechanism called "adjacent cell disturb." This is when part of the charge on one flash cell leaks sideways into an adjoining cell.

As the levels of charge on the floating gates become smaller and smaller, the impact of a few electrons migrating from one floating gate to another becomes more and more significant. A lot of work is going into solving these problems. For instance, SanDisk has been working on a three-bit NAND cell, and absorbed another company, M-systems, who planned to sample a four-bit per cell NAND solution toward the end of 2007.

As if that were not enough, participants in the NAND market are already looking into ways to go beyond four bits per cell. SanDisk is once again a leader in this campaign, having purchased a company called Matrix Semiconductor in 2006. Matrix developed a means of stacking transistors one atop another to get to 8 or even 16 levels, multiplying the amount of memory on a given size chip by the same number. There is a long way to go with technologies like these!

Another approach to multilevel cells
There is a completely different approach to storing multiple bits on a cell that is used by fewer manufacturers but is quite possibly going to find expanded use in the future. This technology goes by different names, the most common being Saifun's NROM, Spansion's MirrorBit, and its near-equivalent technology from Macronix. This technology actually uses a flash cell that is manufactured slightly differently than the typical cell of figure 1 in Part 1. In the typical gate, the floating gate is made of conducting polysilicon. In the MirrorBit cell, an insulating nitride layer replaces the floating gate's polysilicon.

In such a cell, the higher tunneling voltage is applied only on the source and not on the drain. Since the floating gate is an insulator, any charge placed on the floating gate ends up near the source. This means that a different charge can be put on one side of the floating gate or the other simply by swapping the source and the drain with each other.

Reading the cell is a little odd. When a current runs from the source to the drain, a zone grows around the source that is impervious to the charge on the gate. This means that the current from the source to the drain will only be impacted by gate bias that is not near the source. The current will ignore the charge on the floating gate that is close to the source, and will only be impacted by the charge near the drain. Once again, by exchanging the source with the drain, we can choose which side of the cell we want to read, the left or the right.

This is a tidy means of achieving two bits per cell, and Spansion claims that the process is less expensive to manufacture than that of standard floating gate technology. The next question is where to go from here? It is clear that the same trick used to store multiple levels on a conventional floating gate can be used in a NROM cell, and this is exactly what Spansion aims to do, with devices sampling at the writing of this chapter. It would not be surprising to see such a technology further expanded with other existing four-bit schemes to make an eight-bit cell in the future.

Stacking die to achieve higher storage capacity
Apart from schemes to get the most storage on the least amount of silicon is a push to get the most storage in the smallest physical space within the system. This is especially important for portable devices like cellphone handsets and high-capacity flash cards and MP3 players. A common approach to this is to stack memory chips within a package that would normally be used to house a single chip.

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