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Addressing USB 3.0 challenges

12 Oct 2012  | Terrill Moore

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In this realm, microseconds matter. Consider a disk drive capable of 300 megabytes/second throughput, where each transfer moves 1MB. This implies that the system (host and device) must complete at least 900 transfers per second. In the simplest case of sequential access, each transfer must complete in 1,111 microseconds. Suppose that system overhead adds 20 microseconds delay to each transfer. This will drop the number of transfers per second, and we'll only achieve 295 megabytes per second. This may result in a competitive disadvantage, if the competitor can go faster.

Going fast is an issue both of hardware and software. On the hardware side, going fast requires efficient hardware. This is particularly an issue for device implementations. The SuperSpeed device controller must have a flexible DMA engine with scatter/gather support and robust handling of short or zero-length packets. It must also minimize software intervention for "ordinary" events. This will minimize the number of software paths that need to be optimized. Host implementations can rely on the xHCI architecture to take care of most of these issues; although xHCI and system implementations vary in their throughput, the xHCI architecture doesn't require a lot of software intervention in most cases.

However, software must also be efficient. The entire software stack must be designed with a zero-copy architecture, so that the data flows directly to and from the application buffers. The implementation must minimize "round trips," where control flows from the top of the software stack to the bottom and returns. The CPU cache must be carefully managed, especially on ARM processors where concurrency must be managed by system software.

Finally, although SuperSpeed software must be efficient, it must also be polite. USB is frequently not the most important feature of a system. Hundreds of megabytes/second may overwhelm the limited memory systems in embedded systems, and dissipate unwanted power. Host and device software stacks must allow implementers to tune the system to mitigate bus bandwidth and interrupt overhead and control dynamic memory utilization, so that SuperSpeed USB can co-exist with the other applications of a system.

MCCI's TrueTask USB host and device stack, for example, has several ways of tuning the system. All processing is driven from an event queue. Even on a system without an OS; CPU bandwidth can easily be throttled by restricting the number of events processed before yielding the CPU. DMA access is handled via an abstraction layer, with asynchronous callbacks; this allows the system policy manager to manage bus bandwidth by limiting the amount of possible DMA operations outstanding at any given time.

Dynamic memory utilization is especially important on embedded systems—a large device tree with many tiers of hubs can require a lot system memory. For critical systems with limited RAM, this may be unacceptable. TrueTask USB can pre-allocate all needed RAM at boot time, dynamically allocate from a fixed pool, or dynamically allocate from system pool. Pre-allocating at boot time allows for deterministic behavior for a given USB tree size, and for graceful failure if the pre-determined maximum tree size is exceeded. Dynamic allocation results in more efficient memory allocation at the sacrifice of determinism. The two dynamic variants differ in their impact on remaining system memory; the fixed pool reserves a constant amount of memory, increasing predictability.

Support for high-speed in USB 3.0 devices
Device engineers need to remember that every USB 3.0 device has two device controllers: one SuperSpeed, and one high-speed. All SuperSpeed devices have to work with USB 2.0 hosts, not only because the specification requires it, but because the number of USB 2.0 host ports in the market will be significant for several years.

The high-speed device controller hardware must be production quality. It's a good idea to get your USB 3.0 controller from a vendor who has demonstrated experience developing high-performance high-speed device controllers. USB 3.0 device certification for the silicon covers high-speed compatibility, so check for this. But you will still need to make sure that the high-speed device controller is fast and capable enough to keep users satisfied if the device is plugged into a USB 2.0 port.

It is possible to build the SuperSpeed and high-speed device controllers as two completely separate blocks, with minimal integration. However, bear in mind that the device software will then need two software stacks, one for the SuperSpeed block and another for the high-speed block. System software may also need to manage the requirement that the devices disconnect from the high-speed bus when SuperSpeed connect is detected.

USB 3.0 has reached maturity, and is shipping in mainstream systems from the major vendors. Although there are challenges facing adopters, things are now stable enough and well enough understood to allow USB 3.0 to serve as a platform for innovative product development.

About the author
Terrill M. Moore is CEO and founder of MCCI. Terry has 35 years experience designing and implementing computer system software and holds six hardware and software patents. At MCCI, his technical accomplishments have included the architecture and initial implementations of MCCI's USB device and host stacks, as well as MCCI's USB 3.0 host stack for Windows. A recognized expert in Universal Serial Bus (USB) technology, he co-chaired the Communication Device Class Committee of the USB-IF Device Working Group from 2000 to 2005 and again from 2008 to 2011. He is active in various related standards efforts and is a member of the board of directors of Portable Computer and Communications Association (PCCA). He authors an MCCI blog Making Connections.

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