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Ensigma Series4 IP supports 802.11ac

14 Nov 2012

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Imagination Technologies has unleashed the latest generation architecture of its Ensigma universal communications IP core family. According to the company, the Ensigma Series4 IP architecture features a highly scalable multi-core approach for maximum configurability, combined with an ultra-high bandwidth programmable bus fabric and an extremely efficient VLIW-based 4th generation modulation processor with multi-context capabilities. This enables Series4 RPUs to be configured to 4x4 MIMO, 802.11ac and beyond, as well as more than 30 standards for every major 802.11 profile, TV and radio broadcast, Bluetooth and many other broadcast and connectivity communications standards, indicated the company.

Series4 RPUs are offered in a wide spectrum of performance capabilities, ranging from MIMO-capable multi-stream cores featuring dynamic support for mixed simultaneous standards to single-stream configurations that can replace one or more external chips or hard-wired cores.

Ensigma Series4 is geared for markets including TV and set-top boxes, radio (consumer or automotive), tablets/smartphones, connected consumer, industrial and automotive products, and embedded processors powering the Internet of Things.

Ensigma Series4 delivers support for all key standards for: TV including DVB-T2, DVB-T, ISDB-T, SBTVD, ATSC, GB20600-2006 (CTTB), DVB-S2,DVB-S,ISDB-S, DVB-C2, DVB-C, J.83B, ISDB-C; Analogue TV; Mobile TV including DVB-H, T-DMB, 1-Seg ISDB-T; Connectivity including 802.11abgn, MIMO, 802.11n, MIMO 802.11ac, (Complete, Fully Embedded, or Thin MAC with simultaneous Bluetooth); and Radio including DAB/DAB+, HD Radio, 3-seg ISDB-T, ISDB-Tmm, DRM, FM, AM, detailed the company.

The Ensigma Series4 architecture uniquely combines fully programmable modulation and coding processors with multi-standard hardware accelerators and a multi-stream Direct Memory Access (DMA) fabric to yield a power and area optimised multi-standard base band solution. The core modulation and coding processor is complemented by an array of configurable, and in some cases programmable, hardware accelerators implementing functions less suited to software such as signal down-conversion and advanced error correction, and are themselves re-used between standards.

The physical layer technology is complemented within the RPU by an embedded low-power 32bit Meta processor. The Meta processor within the RPU implements high level control APIs, removes system dependencies and performs task such as the WiFi MAC that might otherwise have been implemented on less power-efficient application processors.

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