Path: EDN Asia >> Design Centre >> IC/Board/Systems Design >> Optimise clock trees to meet performance targets
IC/Board/Systems Design Share print

Optimise clock trees to meet performance targets

14 Dec 2012  | James Wilson

Share this page with your friends

Cycle-to-cycle jitter measures the maximum change in clock period between any two adjacent clock cycles, typically measured over 1,000 clock cycles.

Period jitter is the maximum deviation in clock period with respect to an ideal period over a large number of cycles (10,000 clock cycles typical). Both cycle-to-cycle jitter and period jitter are useful in calculating setup and hold timing margins in digital systems, and are often figures of merit for CPU and SoC devices.

Table: Timing component selection criteria.

Phase jitter is the figure of merit for high-speed SerDes applications. It is a ratio of noise power to signal power calculated by integrating the clock single sideband phase noise across a range of frequencies offset from a carrier signal. Phase jitter is especially critical in FPGA and high-speed SerDes clocking applications in which excessive phase jitter can degrade the bit error rate of the high-speed serial interface.

During clock tree design and component selection, it is important to evaluate devices based on maximum jitter performance. Typical jitter specifications do not guarantee device performance over all conditions, including process, voltage, temperature and frequency variation. Maximum jitter provides a more comprehensive specification inclusive of these additional factors.

In addition, take special care to review jitter test conditions on timing device data sheets. Clock jitter performance varies across a wide range of conditions including device configuration, operating frequency, signal format, input clock slew rate, power supply and power supply noise. Look for devices that fully specify jitter test conditions since they guarantee operation over a wider operating range.

Selection criteria for clock and oscillator components

Once the basic clock tree architecture is determined, the next step is component selection. The table summarises the selection criteria that should be used for choosing clock and oscillator components for both free-running and synchronous clock trees. Look for features that simplify clock tree design to minimise bill-of-material (BOM) cost and complexity.

Estimating clock tree iitter
Before a clock tree design is complete, the total clock tree jitter should be estimated to determine if there is sufficient system-level design margin. It is important to note that total clock tree RMS jitter is much less than the simple sum of data sheet jitter specifications from multiple components. The clock tree jitter can be defined by the following:

Note: This equation can be applied to calculating total period jitter and phase jitter, assuming the jitter distributions are Gaussian and uncorrelated. The equation should not be applied to cycle-to-cycle jitter, which is expressed as a peak jitter number and not RMS.

Component jitter can be estimated using data sheet jitter specifications or calculated from phase noise data. Silicon Labs offers a utility for converting clock phase noise to jitter. Be sure to use maximum jitter specifications to generate a conservative estimate of total clock tree jitter.

Simplifying clock trees

Many clock trees require special features in addition to basic clock generation and distribution. For example, the application may require format/level translation (e.g. 3.3 V LVPECL to 2.5 V LVDS), switching between two clocks at different frequencies, clock division, pin-selectable output enable control and CMOS drive strength (output impedance) control for electromagnetic interference (EMI) reduction.

If designed discretely, implementing these functions adds significant cost and complexity to the clock tree design. Silicon Labs has developed a family of Si5330x universal buffers/translators that integrate format/level translation, clock muxing, clock division and other key clock tree building block functions. These devices replace multiple LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single clock buffer IC.

About the author
James Wilson, Director of Marketing, Timing Products, Silicon Laboratories

To download the PDF version of this article, click here.

 First Page Previous Page 1 • 2

Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.

Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming

News | Products | Design Features | Regional Roundup | Tech Impact