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Accelerating pre-silicon validation

20 Feb 2013  | Rajesh Udenia, Rohit Goyal, Neha Singh

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After a design has been instrumented, it is implemented on a device by synthesising and place and route, following which the GUI interface provided by the tool can be used to examine the results. These tools provide observability to any level in the design hierarchy without an extra effort to get them on the design top.

Few such tools utilise the FPGA resources itself like onboard memories, to store the data, and they don't require any external hardware. Such a method for debugging is shown in figure 4.

Figure 4: Debug tools using onboard resources.

But the issue faced by these kinds of tools is unpredictable behaviour from the design after instrumenting the probes with regard to the frequency of operation and routing congestion.

There are also some other tools available that are also real time and provides the flexibility of run time trigger configurability. These tools come with associated hardware which provide the necessary storage for the data hence, do not use any FPGA resources. Such method for debugging is shown in figure 5.

Figure 5: Debug tools using external hardware.


 • This method for debugging can be adopted for designs having relatively large number of I/Os, as it eliminates the need of extracting the internal signals on top of the board.
 • This method can be opted in situations where the design simulates well but once integrated to the FPGA, does not show the expected behaviour. As debugging of such issues require tools which not only offer real time debugging but also have signal probing capabilities.
 • These tools make the debug process relatively easier as they usually dumped the waveforms/data in formats that can be opened using the most common simulation tools.
 • Such debug tools also have the capabilities to store the waveforms captured in their own associated memory and thus generally don't constraint the design by consuming resources of the FPGA board.

 • External hardware and software setup is required.
 • There is a limitation on the number of debug nodes.
 • Visibility of design hierarchy is restricted depending on the memory available for storage of dumped data.
 • Achievable frequency gets reduced.
One of the options to fasten the debug is to create simultaneous builds with instrumenting signals from a particular hierarchy or module so that a test suite could be run on the bit stream with signals from the module or block under debug. This would definitely save time in creating builds only after an issue is encountered in the execution phase.

It is clear that there is no debug technique that can be considered universal and can be used for validation of all designs. There are some limitations and constrains associated with different debug techniques, but still, if chosen wisely, these debug tools/techniques can be really helpful in reducing the debug effort as well as the debug cycle time.

Reduced debug time can be a great milestone to speed up the process of pre-silicon validation which is a primary requirement in order to meet time-to-market demands and still be able to achieve fully functional first-time silicon.

[1] Troy Scott, Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype.

[2] Harald Werner, Debugging methods for FPGAs.

[3] Doug Amos, Austin Lesea, René Richter, FPGA-Based Prototyping Methodology Manual: Best practices in

Design-for-Prototyping (FPMM)

About the authors
Neha Singh is working with Freescale Semiconductor India Pvt Ltd, Noida, India as a Design Engineer and has 2+ years of experience. She is working in Pre-Silicon Validation, FPGA Prototyping and emulation. She has carried out verification of critical IPs. She has also worked on Post-Silicon Validation of Automotive and IMM SoCs.

Rohit Goyal is working with Freescale Semiconductor India Pvt Ltd, Noida, India as a Design Engineer and has 1+ years of experience. He is working in Pre-Silicon Validation, FPGA Prototyping as area of specialisation and has also been involved in verification of some critical IPs.

Rajesh Udenia is working with Freescale Semiconductor India Pvt Ltd, Noida, India as a Design Engineer-III and having 10+years of experience. He is working in Pre-Silicon Validation, FPGA Prototyping as area of specialisation and previously was involved in design development and verification on FPGA of communication networking technologies. He has also worked with CIENA India Pvt. Ltd. and C-DoT.

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