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FPGA-based reference design for smart grid automation

04 Mar 2013

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Altera Corp. has released what it says is a high-availability seamless redundancy (HSR) and parallel redundancy protocol (PRP) reference design geared for smart grid substation automation equipment. In partnership with Flexibilis Oy, they unveiled the IEC 62439-3-compliant reference design that includes Flexibilis Redundant Switch (FRS) IP implemented on an Altera low-power, low-cost Cyclone-class FPGA or Cyclone V SoC.

The Flexibilis HSR/PRP IP included in the reference design is a triple-speed 10/100/1000Mb/s Ethernet Layer 2 switch that is scalable from 3-8 ports and is compliant with the IEC 62439-3 standard. The IP is optimised for an Altera low-power, low-cost Cyclone IV FPGA, Cyclone V FPGA or Cyclone V SoC, which feature an integrated dual-core ARM Cortex-A9 processor sub-system. Cyclone V SoCs enable customers to reduce component costs by implementing their HSR/PRP switch along with the associated software stacks running on the ARM processor sub-system in the FPGA. For timing synchronisation, the HSR/PRP solution supports IEEE 1588 Precision Time Protocol (PTP) Version 2.

Altera and Flexibilis make it easy to implement an FPGA-based HSR/PRP Ethernet switch. Combining Altera FPGAs with the FRS IP provides an easy and cost-effective way to implement highly reliable mission-critical communications systems in smart grid substations by offering no licence negotiation, no up-front licensing costs and no per-unit royalty reporting, the companies indicated.




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