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IP core claims to double eMMC interface performance

05 Mar 2013

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Arasan Chip Systems Inc. has revealed support for the upcoming eMMC 5.0 specification that is proceeding to ratification within the JEDEC standards organisation. The upcoming eMMC standard revision is expected to double the maximum speed of the current eMMC 4.51 devices from 200MB/s to 400MB/s, the company added.

The eMMC total IP solution comprises digital and analogue IP cores, software stack, firmware and a hardware validation platform. The eMMC 5.0 IP core is derived from Arasan's silicon-proven eMMC IP product line. Unlike previous eMMC specifications, the 400MB/s interface will require analogue PHY components. Arasan's eMMC 5.0 core includes an analogue PHY, licensed as GDSII, comprising the 3 DLLs required for tuning, strobe and hold time management. Also included are pads, derived from existing Arasan silicon-proven technology, which support the new performance levels at the required voltage levels.

Arasan's eMMC software stack has been upgraded to support the new specification requirements and a new firmware driver designed to support booting from an eMMC 5.0 device. Completing the Total IP Solution is the hardware validation platform.

Arasan's is engaging with early adopters for licensing of analogue and digital IP cores, Verilog HDL for verification, software stack and firmware and sales of the hardware validation platform.

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