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CMP offers ST analogue 130nm H9A CMOS process prototyping

12 Mar 2013

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The H9A CMOS process (at 130nm lithography node) by STMicroelectronics and Circuits Multi Projets (CMP) is now made available for prototyping to universities, design companies and research labs. The process offers a large panel of analogue and digital devices through CMP-provided silicon brokerage services.

ST is releasing this process technology to third parties as a foundry service for a well-established analogue platform and for new developments in the More than Moore applications such as energy harvesting, autonomous intelligence, and home-automation integrated systems.

The introduction in CMP's catalogue of ST's H9A (and its derivative H9A_EH) process builds on the successful collaboration that has allowed universities and design firms to access leading-edge and previous CMOS generations including 28nm CMOS, 45nm, 65nm, 90nm, and 130nm through the ST Site of Crolles. CMP's clients also have access to 28nm FD-SOI, 65nm SOI and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from ST. More than 200 universities and companies have received the design rules and design kits for the ST 65nm bulk and SOI CMOS processes. Since CMP started offering the ST 28nm CMOS bulk technology in 2011, some 100+ universities and microelectronics companies have received the design rules and design kits, and 30+ integrated circuits (ICs) have already been manufactured. Since CMP introduced the 28nm FD-SOI, 30+ universities and microelectronics companies have received the design rules and design kits.

CMP multi-project
The CMP multi-project wafer service allows organisations to obtain small quantities—typically from a few dozens to a few thousand units—of advanced ICs. H9A design rules and design kits are now available for universities and microelectronics companies and the first requests are already being answered. A run is forecast for September 2013 to carry the first contributions.

ST will propose ULP/ULQC devices (Ultra Low Power, Ultra Low Quiescent Current) in the next Design Kit (DK) generations as this is a requirement for harvesting low-energy sources and for long-life autonomous intelligent systems. One of the world's most advanced 200mm wafer plants, ST's Rousset site has become a centre that provides a technology designed for low consumption and slow duty cycles and attracts innovating contributions and collaborations from the academic research environment While providing additional features in the near future, compatibility with current DK and process will be granted regardless of the technology evolutions in order to keep a stable offer and allow medium- and long-term planning to interested universities and design firms.

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