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Enable sharing with PCI Express

03 Apr 2013  | Krishna Mallampati

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As young children we were taught that sharing is good. The semiconductor industry seems to have forgotten the spirit of that lesson, but one technology that reminds us of what our parents taught us is PCI Express (PCIe). Multiple vendors have tried to use this ubiquitous interconnecting technology to enable the sharing of I/O end-points and, therefore, lowering system costs, power requirements, maintenance, and upgrading needs. PCIe-based sharing of I/O end-points is expected to make a huge difference in the multi-billion dollar data center market.

Shared I/O
Traditional systems currently being deployed in volume have several interconnect technologies that need to be supported. As figure 1 shows, InfiniBand, Fibre Channel and Ethernet are a few examples of these interconnects.

Figure 1: Example of a traditional I/O system in use today.

This architecture has several limitations, including:

 • Existence of multiple I/O interconnect technologies
 • Low utilisation rates of I/O end-points
 • High power and cost of the system due to the need for multiple I/O end-points
 • I/O is fixed at the time of architecture and build... no flexibility to change later
 • Management software must handle multiple I/O protocols with overhead
The architecture is completely disadvantaged by the fact that multiple I/O interconnect technologies are in use, thereby increasing latency, cost, board space, and power. The architecture would at least be partially useful if all the end-points are being used 100%. However, more often than not, they are under-utilised. Customers pay the entire overhead for a limited use of the end-points. The increased latency is because the PCIe interface native in the processors on these systems needs to be converted to multiple protocols. Designers can reduce their system latency by using the PCIe that is native on the processors and converge all end-points using PCIe.

Clearly, sharing I/O end-points (figure 2) is the solution to these limitations. This concept appeals to system makers because it lowers cost and power, improves performance and utilisation, and simplifies design. With so many advantages, it is no surprise that many companies have tried to achieve this; the PCI-SIG, in fact, published the Multi-Root I/O Virtualisation (MR-IOV) specification to achieve this goal. However, due to a combination of technical and business factors, MR-IOV as a specification hasn't really taken off, even though it has been more than five years since it was released.

Figure 2: Example of a traditional I/O system with shared I/O.

Additional advantages of shared I/O are:

 • As I/O speeds increase, the only additional investment needed is to change the I/O adapter cards. In earlier deployments, when multiple I/O technologies existed on the same card, designers would have to re-design the entire system, whereas in the shared-I/O model, they can simply replace an existing card with a new one when an upgrade is needed for one particular I/O technology.
 • Since multiple I/O end-points don't need to exist on the same cards, designers can either manufacture smaller cards to further reduce cost and power, or choose to retain the existing form factor and differentiate their products by adding multiple CPUs, memory and/or other end-points in the space saved by eliminating multiple I/O end-points from the card.
 • Designers can reduce the number of cables that crisscross a system. With multiple interconnect technologies comes the need for different (and multiple) cables to enable bandwidth and overhead protocol. However, with the simplification of the design and the range of I/O interconnect technologies, the number of cables needed for proper functioning of the system are also reduced, thereby eliminating the complexity of the design, in addition to delivering cost savings.

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