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How to debug FPGA-based video systems (Part 1)

16 Jul 2013  | Andrew Draper

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All timing models for a design must pass before it can be used in a production system is used when timing passes only at lower temperatures: a liberal application of freezer spray to the chip can make a design work for a minute or two e often long enough to indicate that timing is the cause of failures.

Fix your design if it does not meet timing
Here we will be referring back to the two basic timing equations earlier. In most chips the propagation delay is significantly larger than the hold time, so the first equation is the harder to satisfy. This equation can always be satisfied by decreasing the clock frequency (increasing the clock period) but this is usually unsatisfactory, especially for video designs where a minimum clock frequency is required to process all the pixels in a frame.

Another method is to buy a chip at a faster speed grade. Unfortunately this has cost implications or is not possible because previously shipped products need to be upgraded. Other methods of making a design meet timing include:

1. inserting buffer registers to reduce the length of combinational paths;

2. changing the layout to place critical registers closer to each other; and

3. reducing the fan out of signals (which can increase switching speed and make the layout simpler).

If the timing tool reports hold-time violations that reducing the clock speed will not fix, design changes are required. Refer to FPGA Design: Best Practices for Team based design (Simpson) ISBNe13: 978-1441963383.

If you are using library components to create your design then the component designer will have already considered these issues and may have included parameters which help their component meet timing (usually in exchange for an increase in size or latency). Many libraries include components called pipeline bridges (or similar names) which can be used to easily insert buffer registers into all the signals of a bus without affecting its behaviour.

Figure 2: Deubg agent for clock sense indication.

The SystemConsole debugger
As we will use SystemConsole as an example of a tool running on a debug host we will now provide a basic introduction. Debug tools usually refer to the system being debugged as the target e the system which you use to debug the target is the debug host.

The host will be connected to the target via one or more debug cables (nowadays these are normally JTAG, USB or Ethernet though debugging over other media is possible). To enable debugging, the system designer places debug agents within the target system (figure 2). These agents are sometimes packaged within other components e for example, most processor components now contain a debug module e or they can be explicitly instantiated by the system designer.

Those debug agents that use a JTAG interface to communicate with the host are automatically connected to the JTAG pins on the device by the Quartus software. In the current Altera software, debug agents using other cables (USB and Ethernet) must be explicitly connected to the pins on the device.

Check that clocks and resets are working
Incorrectly functioning clocks or resets are a common cause of design failures, which should be ruled out early in the debug process e even experienced engineers have wasted hours of time debugging apparently failed systems where the clock has been disabled or the wire supplying the clock signal from a test device to the board has been knocked off.

Other causes of clock failures include Phase locked loops which are unable to lock because their input signal has too much jitter or is outside the acceptable range of input frequencies. Reset signals can also become stuck e either holding part of the design in reset permanently or never resetting it.

If a design is not reset then it does not start in a consistent state, and may get into a state that its designer did not intend. Sometimes a design will get out of these unusual states and sometimes it will become stuck. FPGA designs with reset faults sometimes work because the configuration logic within the FPGA sets most registers to their defined reset state at the end of configuration.

Most debug tools, for example the Altera SystemConsole tool, provide ways to check that clocks are running and resets are behaving correctly. In SystemConsole the explorer window shows a green clock badge on nodes that have a running clock and a red clock badge (with associated tooltip) on nodes which can sense the clock but do not detect it running.

It also provides the jtag_debug service to give scripted access to the clock sensing hardware. The TCL (Tool Command Language) code below shows an example of its use:

set jd [lindex [get_service_paths jtag_debug] 0]

open_service jtag_debug $jd

puts "Clock running: [jtag_debug_sense_clock $jd]"

puts "Reset status: [jtag_debug_sample_reset $jd]"

Part 2 of this series will look into clocked and flow controlled video streams.

This article is from a chapter in Digital Video Processing For Engineers, by Michael Parker and Suhel Dhanani and is used with the permission of the publisher Newnes (Copyright 2013), an imprint of Elsevier Ltd.

About the author
Andrew Draper is a principal design engineer at Altera Corp. and is based in Chesham, Buckinghamshire, United Kingdom. He received his engineering training at Cambridge University and Godalming College before going on to work at Philips Consumer Electronics and Madge Networks.

To download the PDF version of this article, click here.

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