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Questa platform adds software-driven verification

17 Jul 2013

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Mentor Graphics recently announced that intelligent software-driven verification (iSDV) has been added to the Questa functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification.

With the new addition, engineers will find more system level design bugs earlier in the verification process, specifically during simulation or emulation, when they are easier and more cost effective to debug, before they escape into the prototype lab.

"To fully verify our high performance SoC bus fabric sub-systems, we have to generate all kinds of complex traffic scenarios. Using Questa's intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule," said Altera's senior verification architect Galen Blake. "With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence," added Blake.

The Questa iSDV technology aims to address the challenges encountered by engineering teams when verifying multi-core SoC designs. The technology automates the process of writing directed tests in C, creating embedded test programs that run in either the Questa verification or Veloce emulation environments offering scalability across engines.

"Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose," said Mark Olen, verification solutions technologist, Mentor. "Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level."

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