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UMC adopts Cadence DFM signoff for 28nm design

18 Jul 2013

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Cadence Design Systems Inc. has revealed that United Microelectronics Corp. (UMC) has adopted the Cadence "in-design" and signoff design-for-manufacturing (DFM) flows to perform physical signoff and electrical variability optimisation for 28nm designs. The firms stated that the flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs.

Developed in collaboration with UMC, the flows incorporate DFM prevention, analysis and signoff capabilities including Cadence Litho Physical Analyser (LPA), Cadence Pattern Analysis, Cadence Litho Electrical Analyser (LEA) and Cadence Chemical-Mechanical Polishing Predictor (CCP) technologies.

At 28nm and beyond, it is critical to accurately predict and automatically fix DFM "hotspots" to accelerate time-to-yield. UMC joins a growing list of leading foundries standardising on Cadence DFM solutions to boost productivity and yield for customers. The DFM signoff technologies tightly integrate into the Encounter digital and Cadence Virtuoso custom/analogue implementation and sign-off solutions. This solution delivers a "correct-by-design" capability for customers that models and analyses the physical and parametric impact of lithography, CMP and layout dependent effects, and then optimises the implementation to mitigate the physical and electrical variation on the designs, allowing users to reach their time-to-volume goals, indicated the firms.

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