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1T-OTP memory IP tweaked for advanced process chip designs

02 Aug 2013

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Sidense recently debuted its Sidense Hiper Fuse (SHF) one-time programmable (OTP) memory for ICs developed in advanced process at 40nm, 28nm, 20nm and smaller geometries. Sidense SHF 1T-OTP has already been qualified in 40nm processes in both G and LP variants, and is completing qualification in multiple 28nm processes with 20nm qualification to follow. SHF uses include code storage, field-programmable ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.

SHF brings the advantages of the company's 1T-OTP memory to customers developing silicon products in 40nm and more advanced process technologies. In addition to providing small footprints, SHF macros do not require any additional masks or process steps to implement in polysilicon or HKMG advanced processes (gate first and gate last), providing a very cost-effective embedded memory solution. Sidense's patented one-transistor bit cell also provides many advantages in security and reliability when compared to other types of non-volatile memory.

The memory IP boasts fast programming and fast read performance for executing code in-place, read and write operation over -40°C to 125°C, and a comprehensive feature set providing built-in redundancy, programming and test interfaces, error correction, program control, self-test and support for high-security applications. A range of power supply options are also available for in-field programming, supporting both high-performance computing and mobile, power-sensitive applications.

SHF NVM is available with a wide range of 1T-OTP macro configurations up to 1Mbit that can be instantiated multiple times for much larger configurations.

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