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Arasan debuts M-PHY 3.0 IP for mobile applications

10 Oct 2013

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Arasan recently launched an MIPI M-PHY 3.0-compliant IP supporting multiple speed gears and a broad range of high-speed interfaces for mobile applications. The company's MIPI M-PHY version 3.0 multi-gear analogue IP PHY supports a wide selection of protocols including Universal Flash Storage (UFS), Camera Serial Interface 3 (CSI-3), USB Super-speed Inter-chip (SSIC) and M-PCIe interfaces.

The company's M-PHY IP offers support for high-speed GEAR1, GEAR2 and GEAR3 supporting a wide variety of different protocol and performance requirements up to 5.8Gbit/s per lane. In addition, the MIPI M-PHY IP is complaint to MIPI Alliance Standard for M-PHY specification version 3.0, supports M-PHY Type I systems, high-speed differential and low-speed PWM modes, configurable termination, error detection and on-chip clock generation.

"We have been licensing the Arasan M-PHY analogue IP for customers' mobile application processor and memory applications for more than 18 months," stated Andrew Haines, VP of Marketing. "Leveraging our leadership position in deploying M-PHY analogue IP to multiple tier-1 SoC and memory manufacturers, we have assembled a Total IP Solution for UFS consisting of UFS 2.0, UniProSM 1.6, M-PHY 3.0, UFS stack and drivers and a hardware validation platform."

The highly configurable M-PHY analogue IP core enables designers with a scalable solution to easily meet increasing high performance data rates, modular architectures for IP re-use and customer proven silicon IP. Arasan's MIPI M-PHY analogue IP implementation is optimised to support high-performance while meeting the low power, small area and optimised electromagnetic interference (EMI) performance requirements of mobile applications.

Further information on Arasan's MIPI M-PHY version 3.0 multi-gear analogue IP PHY can be found here.

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