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XR9200 coprocessors boast hardware-accelerated encryption

18 Oct 2013  | Julien Happich

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To address the requirements of high performance applications in data analytics, storage, and cloud security markets, Exar has introduced its XR9200 coprocessor family. The company's latest coprocessor line will provide leading-edge compression to remove or minimise costly I/O bottlenecks and enable maximum system throughput with minimum latency.

The XR9200's hardware-accelerated encryption and public key processing enables the secure infrastructure needed to support high transaction throughput and packet-per-second rate required by enterprise, cloud and web-based applications. The family of coprocessors offloads computationally intensive compression and security algorithms from a host CPU and matches the performance of hundreds of enterprise class x86 CPU cores at much lower power and cost.

The chip supports 40Gbit/s of processing throughput with simultaneous compression, encryption and hashing, offering compression ratios comparable to Level 9 gzip. It supports 40,000 operations/s of RSA with 2048 bit keys. Other features include a PCI Express 3.0 host interface supporting 64Gbit/s of bandwidth with 8 lanes and a 40Gbit/s Interlaken interface for external FPGA connection. The device also allows single root I/O virtualisation (SRIOV) with 128 virtual functions to support virtualized I/Os. It can implement gzip, zlib, Deflate, and eLZS, with support for a wide range of symmetric and asymmetric encryption algorithms. Security containment features include a Key Unwrap engine and a Key Encryption Key store with Tamper Zeroisation.

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